Multi-Channel Memory ECC Layout for Multi-Bit Error Correction
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Solution Overview
Problem
High-precision semiconductor memory systems require advanced error correction codes to handle multiple-bit errors effectively, but existing codes like BCH and Reed-Solomon codes increase die size and processing time due to additional check bits.
Innovation Solution
The implementation of multi-channel error correction in semiconductor memory devices, where data bits are distributed across channels with separate ECC processing, allowing for flexible assignment of check bits to support higher error correction capabilities without increasing die size or processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex error correction codes (BCH, Reed-Solomon) are used to correct multiple-bit errors, then error correction capability is improved, but die size and processing time increase
Solution Approach 1:
The patent divides the error correction function into multiple independent channels, each handling a portion of the data bits. Instead of using a single complex code that processes all data together, the system segments data into multiple channels and applies simpler ECC codes to each channel independently, reducing the overall complexity and die size while maintaining multi-bit error correction capability across the entire data set.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one large ECC code covering all data) to a multi-dimensional approach by introducing channel dimensioning. Data is organized across multiple channels, each with its own ECC processing, allowing the system to achieve equivalent or better error correction capability without increasing die size, as the complexity is distributed across multiple simpler parallel processing paths.
2Reliability
If complex error correction codes (BCH, Reed-Solomon) are used to correct multiple-bit errors, then error correction capability is improved, but processing time increases
Solution Approach 1:
By segmenting data into multiple channels with independent ECC processing, the patent enables parallel error correction operations. Each channel processes its portion of the data independently and simultaneously, significantly reducing the total processing time compared to a single sequential processing path, while collectively providing multi-bit error correction capability across the full data set.
Solution Approach 2:
The introduction of channel dimensioning transforms the processing architecture from sequential to parallel execution. Multiple channels operate simultaneously in the temporal dimension, reducing processing time while maintaining the reliability benefits of advanced error correction codes through distributed processing.
3Reliability
If more check bits are added to increase error correction capability, then reliability is improved, but die size increases
Solution Approach 1:
The patent segments the check bit generation and processing across multiple channels, with each channel using a smaller number of check bits for its portion of the data. This distributed approach achieves equivalent overall error correction capability to a single large code but with reduced area per channel, allowing standard cell-based implementation and reducing total die size.
Solution Approach 2:
The patent changes the parameter distribution by reducing the number of check bits per channel while increasing the number of channels. This parameter transformation maintains the product of data protection coverage while optimizing the area efficiency, as each channel's ECC circuitry can be implemented with fewer resources.
Data Source
AI summary
Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.