Multichannel Processor Architecture for Multiprotocol Data Handling
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Solution Overview
Problem
Existing multichannel-multiprotocol processors face high circuit complexity, power consumption, and lack of flexibility in processing data packets with novel protocols, making them inefficient for high data transmission rates and unable to handle data packets with unknown header types.
Innovation Solution
A multichannel processor architecture featuring input and output ports, multiplexers, programmable data processing units, a buffer management unit, a descriptor generator, and a RISC processor that separates data packets into headers and payloads, generates processing instructions, and assembles transmit packets, allowing for flexible processing of multiprotocol data packets with reduced circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full microprocessor with extensive instructions is used for data packet processing, then flexibility in processing multiprotocol data packets is improved, but circuit complexity and chip area increase significantly
Solution Approach 1:
The processor is divided into separate functional units: a RISC processor core for control and protocol handling, dedicated hardware circuits for specific processing tasks (fragmentation, assembly, header processing), and separate buffer memories. This segmentation allows each unit to be optimized independently, reducing overall circuit complexity while maintaining processing flexibility through the RISC processor's programmability.
2Adaptability or versatility
If a full microprocessor with extensive instructions is used for data packet processing, then flexibility in processing multiprotocol data packets is improved, but power consumption increases significantly
Solution Approach 1:
By segmenting the processor into a power-efficient RISC core and dedicated hardware units that perform specific tasks in parallel, the system reduces the power consumption of the main processor while maintaining flexibility. The RISC processor consumes less power than a full microprocessor, and the hardware units only consume power when actively processing specific packet types.
Solution Approach 2:
The patent replaces software-based processing (which would require a full microprocessor) with hardware-based parallel processing units. This substitution of mechanical/computational approaches reduces power consumption by performing processing operations in parallel at the hardware level rather than sequentially through software interpretation.
3Adaptability or versatility
If software implementation of data processing is used, then flexibility in processing multiprotocol data packets is improved, but processing speed decreases for high data transmission rates
Solution Approach 1:
The processing system is segmented into parallel hardware units that can simultaneously process different aspects of data packets (header analysis, payload processing, fragmentation, assembly). This parallel hardware processing achieves high speeds while the RISC processor provides flexible protocol handling through programmability.
Solution Approach 2:
The patent merges hardware parallel processing capabilities with software programmability in a hybrid architecture. The RISC processor provides flexible control and protocol adaptation, while dedicated hardware circuits provide high-speed processing for specific tasks, achieving both flexibility and high processing speed.
4Device complexity
If hardwired data processing circuits are used, then circuit complexity is reduced, but ability to process data packets with unknown header types is lost
Solution Approach 1:
The RISC processor serves as a universal control unit that can be programmed to handle different protocol types and header formats. Combined with programmable buffer management and processing units, this creates a multi-functional system that maintains low circuit complexity while gaining the ability to process unknown or future protocol types through software updates.
Data Source
AI summary
An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.