Multi-Channel SAR ADC Circuit With Shared Comparator Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital conversion circuits, particularly successive approximation register (SAR) ADCs, face challenges in achieving high energy efficiency while maintaining a simple structure and low cost, especially when handling multiple channels simultaneously.
Innovation Solution
The proposed analog-to-digital conversion circuit employs N sampling and conversion modules connected in parallel, each with multiple sampling capacitors, a comparator, and a control module to simultaneously sample and sequentially convert analog signals from N channels, reducing charge loss and improving energy efficiency through a successive approximation method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If N separate ADC circuits are used to simultaneously convert N channels, then conversion accuracy and simultaneity are improved, but circuit complexity and cost increase significantly
Solution Approach 1:
The patent merges N separate ADC conversion functions into a single ADC circuit by having N sampling and conversion modules share one comparator and one control module. The sampling capacitors from different channels are sequentially connected to the shared comparator through conversion switches, allowing one comparator to perform comparisons for all N channels, thus reducing circuit complexity while maintaining conversion accuracy
Solution Approach 2:
The single comparator and control module are designed to serve multiple functions by sequentially processing N different channels. The comparator can compare analog signals from any of the N channels, and the control module can control the conversion switches to connect different sampling capacitors to the comparator, making these components universal rather than dedicated to a single channel
2Measurement precision
If N separate ADC circuits are used to simultaneously convert N channels, then conversion simultaneity is improved, but energy consumption increases
Solution Approach 1:
The patent combines N conversion operations into a single ADC circuit that processes all channels sequentially. By sharing the comparator and control module across all N channels, the total energy consumption is reduced compared to having N separate ADC circuits, while still achieving simultaneous sampling and conversion across all channels through the shared architecture
Solution Approach 2:
The control module periodically controls the conversion switches to connect different sampling capacitors to the shared comparator in sequence. This periodic switching allows the single comparator to process N channels sequentially, reducing energy consumption while maintaining the ability to convert all channels simultaneously through coordinated timing
3Device complexity
If a simple ADC structure is used to reduce cost, then circuit complexity is reduced, but energy efficiency deteriorates
Solution Approach 1:
The patent achieves a simple yet energy-efficient structure by merging N conversion functions into one ADC circuit with shared components. The sampling capacitors are efficiently utilized by sequentially connecting them to the shared comparator, reducing charge loss and improving energy efficiency without requiring complex separate circuits for each channel
Solution Approach 2:
The patent changes the operational parameters by implementing sequential switching of conversion switches that connect sampling capacitors to the comparator. This parameter change in the switching sequence allows the simple shared architecture to achieve high energy efficiency by minimizing charge discharge and reuse of sampling capacitor charges across different channels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances energy efficiency and reduces circuit costs by allowing direct successive approximation conversions on sampling capacitors, achieving efficient multi-channel analog-to-digital conversion with reduced charge loss and improved accuracy.
Implementation Method 1
each of the sampling and conversion modules includes a plurality of sampling capacitors connected in parallel
Implementation Method 2
a comparator connected to the N sampling and conversion modules, configured to compare the second analog signals respectively to obtain comparison signals
Data Source
AI summary
The present disclosure relates to an analog-to-digital conversion circuit comprising: N sampling and conversion modules connected in parallel, configured to simultaneously sample and sequentially convert first analog signals of N channels to output second analog signals, wherein each of the sampling and conversion modules includes a plurality of sampling capacitors connected in parallel, wherein N is an integer greater than 1; a comparator connected to the N sampling and conversion modules, configured to comparing the second analog signals respectively to obtain comparison signals; and a control module connected to the N sampling and conversion modules and the comparator, configured to control the N sampling and conversion modules to output converted digital signals based on the comparison signals.