Multi-Channel SAR ADC Using Shared Sub-DAC to Cut Chip Area
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Solution Overview
Problem
Successive approximation A/D converters face challenges in simultaneously sampling multiple analog signals efficiently, leading to large circuit areas and high manufacturing costs due to the need for multiple capacitive main DACs and sample-and-hold circuits, which also restrict the input voltage range.
Innovation Solution
A successive approximation A/D converter design that uses multiple capacitive main DACs and a single resistive sub DAC, with a successive approximation control circuit to determine bit values, allowing for simultaneous sampling of multiple channels while reducing circuit area and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple successive approximation A/D converters are provided for simultaneous sampling of multiple channels, then the sampling capability is improved, but the chip area and manufacturing cost increase significantly
Solution Approach 1:
The patent merges the sample-and-hold functions into the capacitive main DACs, eliminating the need for separate sample-and-hold circuits. Multiple A/D converters share a common resistive sub DAC and control logic, reducing redundant components while maintaining simultaneous sampling capability across multiple channels
Solution Approach 2:
The capacitive main DACs serve dual functions: they act as both sample-and-hold circuits during the sampling phase and as main DACs during the conversion phase. The resistive sub DAC is shared across all channels for low-order bit generation, making the system more compact and cost-effective
2Measurement precision
If multiple capacitive main DACs with sample-and-hold circuits are used for each channel, then the A/D conversion accuracy is maintained, but the circuit complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the sample-and-hold functionality directly into the capacitive main DAC structure, eliminating separate sample-and-hold circuits. The control logic and resistive sub DAC are shared across all channels, reducing overall circuit complexity while preserving high-resolution conversion capability through the two-stage architecture
Solution Approach 2:
The A/D conversion process is segmented into two stages: high-order bit determination by capacitive main DACs and low-order bit determination by the shared resistive sub DAC. This segmentation allows each component to be optimized for its specific function while sharing common resources
3Productivity
If traditional sample-and-hold circuits are used for each channel, then simultaneous sampling is achieved, but the input voltage range is restricted
Solution Approach 1:
By merging the sample-and-hold function into the capacitive main DACs, the circuit eliminates the need for separate amplifiers in the sample-and-hold stage, thereby extending the input voltage range to include signals near the power rails while maintaining simultaneous sampling capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves efficient three-channel simultaneous sampling with reduced circuit area and cost, while enabling wider input voltage range and flexible control modes, including sequential and concurrent sampling and conversion processes.
Implementation Method 1
In the successive approximation A/D converter of FIG. 1, the capacitive main DAC has the responsibility of sampling and holding an analog signal
Implementation Method 2
a resistive sub DAC (SDAC) and a switch array (SS0 to SS31)... determines the values of the low-order five bits using the sub DAC
Data Source
AI summary
A successive approximation A/D conversion circuit for simultaneously sampling N channels of analog signals and for A/D converting the sampled analog signals, includes: N capacitive main DACs; a resistive sub DAC; N comparators; and a successive approximation control circuit, wherein the successive approximation control circuit determines high-order bit values of A/D conversion results of the N channels of analog signals by controlling the N capacitive main DACs and the N comparators, and determines low-order bit values of the A/D conversion results of the N channels of analog signals by controlling the resistive sub DAC and the N comparators.