Multichannel Signal Generator Phase Control at High Clock Speeds

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Solution Overview

Problem

Conventional signal generators face instability in synchronized signal output at high clock speeds, failing to maintain stable operation and generate user-defined phase differences between channels, especially at frequencies above 100 MHz.

Innovation Solution

The signal generator employs clock phase shifters to control phase relationships between channels, using phase comparators and controllers to generate phase-shifted clocks, allowing for higher time resolution by combining output signals with non-overlapping data bits and reference levels, and utilizing digital-to-analog converters with zeroing stages to produce signals with multiple levels in a single clock cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If clock speed is increased to generate faster signal outputs, then productivity is improved, but stability of synchronized signal output deteriorates

Engineering Contradiction:
Improvesignal output speedVSAvoidstability of synchronized signal output
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the single clock signal distribution into separate clock paths for each channel, with individual phase control for each channel. This segmentation allows each channel to be independently phase-adjusted, preventing the synchronization instability that occurs when a single clock is distributed to multiple channels at high speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic phase adjustment capability where the phase of each channel's clock can be independently controlled and adjusted. This dynamic control allows the system to maintain stable synchronization even at high clock speeds by compensating for phase variations in each channel individually.

Inventive Principle:
Principle #15Dynamics

2Reliability

If conventional clock synchronization is used to maintain stable operation, then reliability is improved, but phase control flexibility and time resolution deteriorate

Engineering Contradiction:
Improvestable circuit operationVSAvoiduser-defined phase difference capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic phase shifters for each channel that can be controlled to provide user-defined phase differences. This allows the system to maintain stable operation through controlled phase relationships while simultaneously providing the flexibility to generate any required phase configuration between channels.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the phase parameter of each channel's clock independently through phase shifters. By controlling the phase parameter dynamically, the system achieves both stable operation (through controlled phase relationships) and user-defined phase differences (through adjustable phase parameters).

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If clock pulses are provided intermittently to control output timing, then ease of operation is improved, but measurement precision of phase relationships deteriorates

Engineering Contradiction:
Improveoutput start controlVSAvoidphase relationship accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent provides clock signals continuously to each channel rather than intermittently. This continuous clock provision maintains stable phase relationships and enables precise phase measurement and control, while the output timing is still controllable through phase shifter adjustment rather than clock gating.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS7562246B2Phase controllable multichannel signal generator
Publication Date: 2009.07.14 TEKTRONIX INC
  • US7562246B2 patent drawing
  • US7562246B2 patent drawing
  • US7562246B2 patent drawing

AI summary

A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.