Multi-Channel Transistor Gate Cut Layout for Defect-Free Removal
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Solution Overview
Problem
The increasing integration level and downscaled nature of integrated circuit devices lead to a short channel effect in transistors, deteriorating the reliability of these devices, and existing methods for removing sacrificial gate electrodes in gate-all-around transistor structures face challenges due to the decreasing distance between gate cut insulating patterns and semiconductor patterns, resulting in product defects.
Innovation Solution
The integrated circuit device incorporates a thick sacrificial insulating layer pattern that serves as a self-aligning mask for forming the gate cut insulating pattern, allowing for easier removal of the sacrificial gate line without the need for precise alignment, thereby reducing the risk of defects during the sacrificial gate electrode removal process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration level is increased and devices are downscaled to meet increasing demand, then productivity and integration density are improved, but short channel effect occurs which deteriorates reliability
Solution Approach 1:
The gate electrode is divided into multiple segments separated by gate cut insulating patterns, allowing independent control and removal of each gate segment. This segmentation enables the gate to conform to the multi-bridge channel structure while maintaining electrical isolation between channels, thus achieving high integration density without compromising transistor reliability through short channel effects
Solution Approach 2:
The patent implements a gate-all-around structure where the gate electrode completely surrounds each semiconductor pattern (nanosheet) in a nested configuration. This nested geometry provides superior electrostatic control over the channel, effectively suppressing short channel effects and maintaining transistor reliability at scaled dimensions while achieving high integration density
2Productivity
If the distance between gate cut insulating pattern and semiconductor pattern is decreased to achieve higher integration, then productivity is improved, but the removal of sacrificial gate electrode becomes difficult resulting in product defects
Solution Approach 1:
A thick sacrificial insulating layer pattern is introduced as an intermediary element positioned between the gate cut insulating pattern and the semiconductor pattern. This intermediary layer serves as a self-aligning mask that facilitates the removal of sacrificial gate lines by providing a sufficient process margin, enabling easier removal despite the decreased distance required for high integration density
Solution Approach 2:
The thick sacrificial insulating layer pattern is formed in advance before the gate electrode deposition, creating a pre-positioned self-aligning mask structure. This preliminary action establishes the correct spatial relationship and provides adequate process window for subsequent sacrificial gate line removal, preventing manufacturing defects while maintaining high integration density
Data Source
AI summary
In some embodiments, an integrated circuit device includes a substrate, a fin-type active region on the substrate that extends in a first direction, a plurality of semiconductor patterns spaced apart from an upper surface of the fin-type active region and include a channel region, a gate electrode, and a gate cut insulating pattern. The gate electrode extends in a second direction on the fin-type active region and is disposed between the plurality of semiconductor patterns. The gate electrode includes a first sidewall extending in the second direction and a second sidewall extending in the first direction. The gate cut insulating pattern is on a second sidewall of the gate electrode. An upper portion of the gate cut insulating pattern is wider in the second direction than a lower portion of the gate cut insulating pattern. A portion of a sidewall of the gate cut insulating pattern is curved.