Multi-Channel TVS Interconnect Layout for Low Capacitance
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Solution Overview
Problem
Existing transient voltage suppressor diodes have high capacitance and large device packages due to non-optimal interconnections, which can lead to inefficiencies in protecting electronic devices from transient voltage spikes.
Innovation Solution
The design incorporates a semiconductor epitaxial layer with laterally arranged fingers of different conductivity types, featuring a silicon controlled rectifier (SCR) and junction diode portions, with optimized metal layer configurations to reduce parasitic capacitance and improve current handling, allowing for a more compact and efficient transient voltage suppression device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interconnection designs are used in TVS devices, then the device provides adequate voltage suppression, but the capacitance is high and the package size is large
Solution Approach 1:
The TVS device is segmented into multiple independent channels, each with its own set of fingers and interconnections. This segmentation allows each channel to be optimized independently, reducing the overall capacitance while maintaining adequate suppression capability across multiple protection channels
Solution Approach 2:
The patent transitions from planar interconnections to three-dimensional vertical interconnections by stacking metal layers above the epitaxial layer. This dimensional change allows interconnections to be routed vertically through vias, reducing the lateral footprint and enabling a more compact package size
2Reliability
If traditional interconnection designs are used in TVS devices, then the device provides adequate voltage suppression, but the capacitance is high
Solution Approach 1:
The harmful parasitic capacitance is extracted and minimized by removing unnecessary interconnection elements and optimizing the remaining interconnections. The patent extracts only the essential interconnections needed for voltage suppression, eliminating excess capacitance that would degrade performance
Solution Approach 2:
By moving interconnections to the vertical dimension with stacked metal layers, the patent reduces the lateral area of interconnections, thereby reducing parasitic capacitance. The vertical via connections minimize the overlapping area between conductive elements, reducing capacitive coupling
3Quantity of substance
If optimized metal layer configurations are used, then capacitance is reduced and current handling is improved, but the device complexity increases
Solution Approach 1:
Multiple metal layers are merged and interconnected through vias to form a unified three-dimensional interconnection network. This merging approach consolidates the complexity into a systematic layered structure that, while more complex than single-layer designs, provides systematic benefits in capacitance reduction and current handling
Solution Approach 2:
The optimized metal layer configuration serves multiple functions simultaneously: it provides low-capacitance interconnections, enhances current handling capability through parallel conduction paths, and enables compact packaging. This multi-functionality justifies the increased structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved design achieves lower capacitance and a more compact package, effectively protecting electronic devices from transient voltage spikes while reducing voltage and enhancing current handling capabilities.
Implementation Method 1
featuring a silicon controlled rectifier (SCR) and junction diode portions, with optimized metal layer configurations to reduce parasitic capacitance
Implementation Method 2
Components used to protect against transients include decoupling capacitors, Zener diodes, avalanche diodes, metal oxide varistors, poly switches and transient voltage suppressor diodes
Data Source
AI summary
A transient voltage suppressing device includes a plurality of fingers arranged laterally along a major surface of an epitaxial layer. The plurality of fingers includes fingers of a first type and fingers of a second type. The first type and second type of fingers each include a silicon controlled rectifier (SCR) region and a junction diode region. The plurality of fingers of the second type are conductively coupled together by a second metal layer disposed over top a first metal layer and electrically insulated from the first metal layer. The first metal layer conductively couples the SCR region and junction diode region of the first type of finger.