Multi-Chip Package With Bonded Heat Spreader for Low Thermal Resistance
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Solution Overview
Problem
Multi-chip IC packages face challenges with structural/mechanical strength and thermal performance due to thin metallization layers and poor thermal conductivity between IC chips, leading to cracking and hot spots, which complicates integration with host substrates.
Innovation Solution
A bonded integrated heat spreader is directly attached to each IC chip using a thin bond line, enhancing mechanical strength and thermal conductivity, and interconnected through redistribution layers on a sacrificial interposer, which is later removed to expose the RDL structure for further interconnects and assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple IC chips are assembled into a multi-chip unit with thin metallization layers for electrical interconnection, then integration density and electrical connectivity are improved, but structural/mechanical strength deteriorates leading to cracking
Solution Approach 1:
The patent employs a composite structure combining thin metallization layers for electrical interconnection with additional structural support layers. The multi-layer construction integrates fragile conductive paths with mechanically robust materials, allowing the assembly to maintain both high integration density and adequate structural strength to prevent cracking during handling and operation.
Solution Approach 2:
The patent divides the interconnection structure into multiple discrete layers, separating the electrical function (thin metallization) from the mechanical support function (thicker structural layers). This segmentation allows each layer to be optimized independently - the metallization for electrical performance and the structural layers for mechanical strength - resolving the contradiction between integration density and structural integrity.
2Productivity
If multiple IC chips are assembled into a multi-chip unit, then functional integration is improved, but thermal performance deteriorates due to poor thermal conductivity between chips
Solution Approach 1:
The patent introduces thermal interface materials as intermediary substances between adjacent IC chips. These materials serve as thermal conduits, bridging the thermal gap that would otherwise exist between chips with different thicknesses and materials. The thermal interface material has optimized thermal conductivity to facilitate heat transfer across the chip interfaces, preventing hot spot formation while maintaining the functional integration benefits of the multi-chip architecture.
Solution Approach 2:
The patent addresses thermal performance by changing the thermal conductivity parameter of the interface regions between chips.通过使用具有不同导热系数的材料（如导热硅脂、导热垫等），在芯片之间建立有效的热传导路径，从而改善整体热性能，防止热点产生。
3Adaptability or versatility
If IC chips of differing thicknesses are assembled together, then design flexibility is improved, but thermal conduction deteriorates due to increased material thickness between chips
Solution Approach 1:
The patent compensates for varying chip thicknesses by adjusting the thermal interface material parameters - specifically selecting materials with appropriate thickness and thermal conductivity to maintain consistent thermal performance across all chip interfaces. This allows the assembly to accommodate design flexibility with different chip specifications while preserving adequate thermal conduction pathways.
Solution Approach 2:
The patent applies different thermal interface materials or different thicknesses of interface materials at different locations between chips, matching the local thermal requirements. Where chips have greater thickness variations, enhanced thermal interface solutions are applied locally to ensure adequate heat transfer, while maintaining overall design flexibility for heterogeneous chip assemblies.
4Temperature
If thin bond lines are used to attach heat spreader to IC chips, then thermal resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the bond line thickness parameter to achieve an optimal balance between thermal performance and manufacturability. By carefully selecting and controlling the thickness of the thermal interface material between the heat spreader and IC chips, the design minimizes thermal resistance while establishing achievable tolerances for standard manufacturing processes, avoiding excessively tight precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves both mechanical and thermal performance by providing a robust and efficient heat dissipation mechanism, reducing warpage and hot spots, and enabling effective integration of multi-chip units with host substrates.
Implementation Method 1
thermal performance because, compared to a monolithic IC chip, the various small IC chips assembled together are less capable of spreading heat across the assembly due, at least in part, to relatively poor thermal conductivity in regions between the individual IC chips
Data Source
AI summary
A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.