Multi-Chip Cluster Architecture With Cache-Coherent Serial Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing distributed computing architectures for autonomous robotic systems, such as autonomous vehicles, fail to meet performance and safety requirements due to the large amount of sensor data processing needed in real-time.
Innovation Solution
A scalable, configurable chip architecture is implemented with a first and second cluster of multi-chip modules connected by a high-speed serial computer expansion bus, enabling cache coherency across serial bus interconnects without specialized modifications, allowing faster memory access and shared data processing among processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing distributed computing architectures are used to process sensor data, then the system can handle basic computing tasks, but the processing speed and performance are insufficient to meet real-time requirements for autonomous robotic systems
Solution Approach 1:
The system divides the computing architecture into multiple independent chip modules, each capable of processing specific sensor data streams. This segmentation allows parallel processing of different data types (e.g., LIDAR, camera, radar) simultaneously, dramatically increasing overall processing throughput and reducing real-time delays in autonomous vehicle decision-making
Solution Approach 2:
The patent transitions from a single-processor distributed architecture to a multi-chip module architecture with three-dimensional interconnects. By adding spatial dimensions to the computing architecture (multiple chips stacked and interconnected), the system achieves exponential increases in processing capacity while maintaining compact form factor, enabling real-time handling of massive sensor datasets
2Productivity
If multiple processors are used to increase processing power, then more functions can be processed in parallel, but data consistency and cache coherency become difficult to maintain
Solution Approach 1:
The patent introduces a cache coherency interconnect as an intermediary mechanism between multiple chip modules. This interconnect maintains unified virtual memory addressing and ensures cache coherency across all processors, allowing parallel processing while guaranteeing data consistency. The interconnect acts as a mediator that coordinates memory access and data sharing without requiring complex software-based synchronization
Solution Approach 2:
The cache coherency interconnect serves multiple functions simultaneously: it provides high-speed data communication between chips, maintains cache coherency, enables unified memory addressing, and supports both coherent and non-coherent access modes. This multi-functional design simplifies the overall system architecture while ensuring reliable parallel processing across diverse workloads
3Adaptability or versatility
If software-based data management is used to maintain data consistency across processors, then flexibility is maintained, but processing overhead increases and performance decreases
Solution Approach 1:
The patent replaces software-based data management mechanisms with hardware-based cache coherency protocols implemented in the interconnect. This substitution eliminates the overhead of software context switching, memory barriers, and synchronization primitives, while maintaining data consistency through hardware-enforced cache coherence. The result is dramatic performance improvement with minimal impact on programming flexibility
4Ease of operation
If a unified memory system is implemented across multiple processors, then data sharing is simplified, but access speed and bandwidth requirements become extremely demanding
Solution Approach 1:
The unified memory system is segmented across multiple chip modules, with each chip having its own local memory resources. The interconnect provides high-bandwidth pathways for memory access between chips, enabling unified virtual addressing while maintaining fast local access. This segmentation allows the system to provide unified memory semantics without requiring all processors to access a single centralized memory pool, thus preserving speed
Solution Approach 2:
The patent implements memory copy mechanisms through the cache coherency interconnect, allowing processors to efficiently replicate data across chip boundaries when needed. The hardware-managed copy operations occur in parallel without blocking processor execution, and the interconnect caches copied data to minimize repeated transfer overhead, maintaining both simplicity of data sharing and high access speeds
Data Source
AI summary
Provided are systems and methods for a scalable configurable chip architecture. The system includes a first cluster and a second cluster multi-chip modules, and a data network coupling the first cluster to the second cluster. Each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chips coupled together by a first interconnect, each chip of the first plurality of chips configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle (AV). Each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chips coupled together by a second interconnect, each chip of the second plurality of chips configured to facilitate processing of at least one function of a second set of functions of the AV.