Multi-Chip Clock Synchronization Using PLL Time Digitization

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Solution Overview

Problem

Current distributed timing synchronization methods in sensor systems, such as PET, LiDAR, and FLIM, fail to achieve picosecond time measurement accuracy due to manufacturing variations, temperature, and power supply voltage mismatches, making it difficult to synchronize multiple sensor chips reliably.

Innovation Solution

A sensor network with a sensor controller and daisy-chained sensor modules using custom integrated circuits with Phase-Locked Loop (PLL) technology for precise time digitization and synchronization, allowing for picosecond accuracy across multiple chips, even with voltage and temperature variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If passive clock distribution with matched-length transmission lines is used, then device complexity is reduced, but measurement precision deteriorates due to manufacturing variations and environmental mismatches preventing picosecond synchronization accuracy

Engineering Contradiction:
Improvesynchronization system complexityVSAvoidtime synchronization accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements an active feedback-based synchronization system where each sensor chip measures its actual clock signal arrival time and compares it with reference timing. The system continuously adjusts timing offsets based on measured deviations, compensating for manufacturing variations and environmental changes. This feedback mechanism enables picosecond-level synchronization accuracy despite using simple matched-length transmission lines without complex calibration procedures.

Inventive Principle:
Principle #23Feedback

2Productivity

If more sensor chips are added to improve system sensitivity and measurement throughput, then productivity increases, but reliability deteriorates due to accumulated timing mismatches and difficulty in maintaining synchronization across additional chips

Engineering Contradiction:
Improvemeasurement throughputVSAvoidsynchronization reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the synchronization problem into independent per-chip measurements rather than requiring global calibration of the entire multi-chip system. Each sensor chip autonomously measures its own timing offset relative to the reference clock, allowing chips to be added, removed, or replaced without affecting other chips. This segmentation enables reliable scaling to large numbers of sensor chips while maintaining picosecond synchronization accuracy across the expanded system.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If extensive calibration procedures are implemented to achieve picosecond synchronization accuracy, then measurement precision improves, but ease of operation deteriorates due to difficult implementation and complex calibration requirements

Engineering Contradiction:
Improvetime measurement accuracyVSAvoidsynchronization implementation ease
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The patent implements a self-calibrating synchronization system where each sensor chip autonomously performs its own timing offset measurement and correction without requiring external calibration equipment or complex manual procedures. The chips automatically measure their clock signal arrival times, calculate timing offsets, and adjust their operation accordingly. This self-service approach achieves picosecond synchronization accuracy while maintaining simple operation and easy system expansion.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables reliable synchronization of sensor modules to picosecond accuracy, improving spatial resolution and measurement throughput by correcting for chip-to-chip mismatches and environmental variations, enhancing the precision of time-of-flight measurements in sensor applications.

Implementation Method 1

Each sensor chip includes a time stamping circuit with a phase-locked loop (PLL) that is locked to a system reference clock

Methodology Applied
Scientific EffectPhase-Locked Loop:

Implementation Method 2

The PLLs all use the same frequency divider ratio so that the VCOs all generate the same frequency even though the VCO frequencies may drift with voltage and temperature

Methodology Applied
Scientific EffectVoltage-Controlled Oscillator:

Data Source

PatentUS12166570B2High precision multi-chip clock synchronization
Publication Date: 2024.12.10 ANACAPA SEMICONDUCTOR
  • US12166570B2 patent drawing
  • US12166570B2 patent drawing
  • US12166570B2 patent drawing

AI summary

A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.