Multi-Chip Clock Synchronization Using Low-Frequency Reference Clocks
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Solution Overview
Problem
Existing multi-chip clock synchronization methods increase input/output operating frequency and power consumption due to shared oscillation frequency, necessitating a solution to reduce these costs and consumption.
Innovation Solution
A multi-chip clock synchronization device and method that individually supplies a low-frequency reference clock to each chip, which is then multiplied to generate a shared target clock, reducing operating frequency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple chips share a common clock source (external oscillator or master chip oscillator), then clock synchronization between chips is achieved, but input/output operating frequency and power consumption increase
Solution Approach 1:
The patent divides the clock generation function into multiple independent segments, with each chip containing its own oscillator and clock generation circuitry. Instead of one centralized clock source serving all chips, each chip generates its own clock signals locally, eliminating the need for high-frequency shared clock distribution and reducing overall power consumption while maintaining synchronization through coordinated generation timing.
2Reliability
If multiple chips share a common clock source, then clock synchronization between chips is achieved, but input/output operating frequency increases
Solution Approach 1:
The patent segments the clock distribution system into individual chip-level generators, allowing each chip to operate at optimized local frequencies rather than being constrained by a shared high-frequency clock distribution network. This reduces the required input/output operating frequency for clock signals while maintaining synchronization.
Solution Approach 2:
The patent introduces intermediary clock generation circuits within each chip that translate a lower-frequency reference signal into the required higher-frequency operating clocks locally. This intermediary approach allows the external or master reference clock to operate at lower frequencies while each chip generates its own high-frequency clocks, reducing overall system I/O frequency requirements.
Data Source
AI summary
The present disclosure relates to a multi-chip clock synchronization device and a method capable of reducing an operating frequency and power consumption when a plurality of chips share clocks for multi-chip clock synchronization, which may include a reference clock supply unit connected to a plurality of chips and supplying a reference clock of a first frequency to each chip and a target clock generation unit generating a target clock of a second frequency based on the reference clock of the first frequency, wherein the reference clock supply unit may generate the reference clock of the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each chip, and the target clock generation unit may multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is input to generate the target clock of the second frequency.