Multi-Chip Clock Alignment Using DPLL Reflected Signal Feedback
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Solution Overview
Problem
Existing digital phase lock loops (DPLLs) require external reference signals to align chip internal clocks, which can be impractical and lead to synchronization issues due to uncorrectable differences in board-level layout.
Innovation Solution
Implementing DPLLs within a clock distribution block to automatically phase align clock signals across multiple chips using point-to-point un-terminated transmission lines and digital variable delay lines, without external reference signals, by utilizing feedback signals and high-threshold input buffers to synchronize clock transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external reference signals are used to synchronize clocks across multiple chips, then clock alignment can be achieved, but board-level layout complexity increases and synchronization reliability decreases due to uncorrectable differences in signal paths
Solution Approach 1:
The patent extracts the reference signal generation function from external sources and places it within each chip's local clock distribution block. Each chip independently generates its own reference signal locally, eliminating the need for external reference signals and complex board-level routing while maintaining synchronization capability through the feedback mechanism
Solution Approach 2:
The patent implements a feedback mechanism where the output clock signal is fed back to the input through the transmission line and variable delay line. The control logic compares the phase of the feedback signal with the reference signal and adjusts the delay to achieve phase alignment, enabling automatic synchronization without external references
2Reliability
If external reference signals are used for multi-chip clock synchronization, then clock alignment is possible, but the system becomes sensitive to board-level signal path variations
Solution Approach 1:
Each chip serves itself by generating local reference signals and using its own output clock signal as the feedback reference. The system becomes self-contained and immune to external interference or board-level variations, as each chip independently establishes its own synchronization reference without relying on external signal paths
Solution Approach 2:
The variable delay line acts as an intermediary that compensates for transmission line delays. By introducing adjustable delay in the feedback path, the system equalizes the total loop delay for all chips, ensuring that chips at different distances from the clock distribution block achieve synchronized clock transitions
3Reliability
If dedicated external clock signals are used to synchronize multiple chips, then proper clock alignment can be ensured, but the number of external connections and board-level complexity increases
Solution Approach 1:
The output clock signal serves multiple functions simultaneously: it drives the target chip's logic and feeds back as the reference signal for phase alignment. This multi-functionality eliminates the need for separate dedicated reference signal connections, reducing the number of external connections while maintaining synchronization capability
Solution Approach 2:
The patent merges the clock output function and reference signal function into a single signal path. The same transmission line carries both the clock signal to the target chip and the feedback reference signal, consolidating what would traditionally require separate connections into one shared path
Data Source
AI summary
This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of clock signals at a plurality of clock pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted clock signal's reflected signal as a tuning reference.