Multi-chip Device Power Down Contention Current Reduction
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Solution Overview
Problem
Multi-chip devices face challenges in reducing contention current during power down due to differences in processing characteristics among chips, leading to voltage discrepancies and potential damage from high contention current.
Innovation Solution
A multi-chip device configuration that includes a power management module with detector circuits and logic circuits to generate pull-up signals, aligning node voltages in the configurable interconnect network by pulling them up to the interconnect power supply voltage when any chip reaches its trip voltage, thereby reducing or avoiding contention current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If standard power down sequence is used in multi-chip devices, then power is shut off, but voltage discrepancies occur between chips leading to high contention current
Solution Approach 1:
The detector circuit detects the power voltage presence before the power down sequence completes, and the pull-up circuit proactively pulls the node voltage to the power supply voltage in advance. This preliminary action ensures voltage alignment occurs before power is fully shut off, preventing contention current and potential chip damage during the power down transition.
2Loss of energy
If power is shut off during power down, then energy consumption stops, but voltage alignment is lost causing contention current
Solution Approach 1:
The pull-up circuit acts as an intermediary between the power supply circuit and the configurable interconnect network. It maintains voltage alignment by actively pulling the node voltage to match the power supply voltage during the power down transition, mediating the voltage discrepancy that would otherwise occur between chips with different processing characteristics.
3Reliability
If detector circuit monitors power voltage presence, then voltage alignment can be maintained, but device complexity increases
Solution Approach 1:
The detector circuit on each chip autonomously detects the presence of power voltage on its own chip, and the pull-up circuit self-regulates to maintain voltage alignment without requiring external control signals from other chips. This self-service approach simplifies the overall system control while maintaining reliable voltage alignment during power down sequences.
Data Source
AI summary
Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.