Multi-Chip Data Transfer Layout for Diagonal Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in providing effective inter-chip communication, particularly when chips are placed on diagonal lines, as it becomes difficult to route wires between them, leading to issues with signal skew and layout design.
Innovation Solution
A semiconductor device configuration with four chips mounted on a substrate, where each chip has a transferring circuit to facilitate data exchange between adjacent chips, including those on diagonal lines, using signal lines that are routed along facing edges to reduce skew and improve timing design, allowing for efficient data transfer and common layout design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chips are placed on diagonal lines of the substrate, then the substrate area utilization is improved, but it becomes difficult to route wires between the chips
Solution Approach 1:
The patent introduces intermediate chips (second and fourth chips) positioned between the diagonally placed first and third chips. These intermediate chips serve as mediators that receive data from one diagonal chip and transfer it to the other diagonal chip through adjacent edge connections, thereby enabling wire routing between diagonal chips without requiring direct diagonal wire paths across the substrate.
2Reliability
If wires are routed between diagonally placed chips, then inter-chip communication is achieved, but signal skew increases due to unequal wire lengths
Solution Approach 1:
The patent segments the direct diagonal communication path into two separate adjacent-edge paths by introducing intermediate chips. The data transmission from diagonal chip A to diagonal chip B is divided into two segments: first from chip A to intermediate chip, then from intermediate chip to chip B. This segmentation allows each segment to use equal-length wire routing along adjacent edges, thereby reducing overall signal skew while maintaining communication reliability.
3Reliability
If transferring circuits are added to facilitate diagonal chip communication, then inter-chip data transfer is improved, but device complexity increases
Solution Approach 1:
The intermediate chips are designed with universal transferring circuits that can handle data transmission from any adjacent chip to any other adjacent chip. The same chip structure and circuit design can be replicated for all intermediate positions in the multi-chip module, allowing a single chip design to serve multiple functions in different positions, thereby reducing overall device complexity through standardization.
4Area of stationary object
If chips are arranged in a compact layout, then substrate area is reduced, but layout design difficulty increases
Solution Approach 1:
The patent employs an asymmetric chip arrangement where chips are positioned at the corners and edges of the substrate rather than in a symmetric grid pattern. This asymmetric layout, with chips placed to maximize adjacent edge connections while maintaining compact area utilization, simplifies the routing design by creating natural communication paths along the substrate edges, thereby reducing layout design difficulty despite the compact arrangement.
Data Source
AI summary
A semiconductor device includes a first chip, a second chip, a third chip, a fourth chip, and a substrate. The first to fourth chips are mounted on the substrate. The first chip is placed adjacent to the second chip and the fourth chip. The third chip is placed adjacent to the second chip and the fourth chip at a position different from that of the first chip. The second chip has a first transferring circuit that transfers data from the first chip to the third chip, and the fourth chip has a second transferring circuit that transfers data from the third chip to the first chip.