Multi-Chip Semiconductor Packaging With Bump-Free Direct Bonding

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving high performance and compactness due to the limitations of traditional bump-based connections, which hinder thermal conductivity and integration efficiency.

Innovation Solution

The development of a packaged semiconductor device that connects multiple semiconductor chips via direct bonding without bumps, utilizing a structure with bond pads and insulation layers to enhance thermal conductivity and integration, allowing for smaller bond pads and improved speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If traditional bump-based connections are used to connect semiconductor chips, then the connection structure is established, but thermal conductivity is reduced due to polymer layers with low thermal conductivity

Engineering Contradiction:

Improvethermal conductivityVSAvoidconnection structure

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The patent removes the polymer layer from the connection structure between semiconductor chips, eliminating the thermal barrier that low thermal conductivity polymer layers created. This extraction of the harmful element directly improves thermal conductivity while simplifying the overall connection structure.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a composite connection structure consisting of a first connection structure made of a first material and a second connection structure made of a second material with different properties. This composite approach allows optimization of thermal conductivity by selecting materials with appropriate thermal properties for different functional requirements.

Inventive Principle:

Principle #40Composite materials

2Productivity

If bump-based connections are used, then mechanical connection is achieved, but bond pad size must be larger reducing integration efficiency

Engineering Contradiction:

Improveintegration efficiencyVSAvoidbond pad area

Core Design Contradiction:

ProductivityVSArea of moving object

Solution Approach 1:

The patent replaces the traditional bump-based mechanical connection system with a direct bonding system where bond pads are connected without intermediate bumps. This substitution eliminates the need for large bump structures, allowing bond pads to be significantly smaller and improving integration efficiency.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Temperature

If direct bonding without bumps is used, then thermal conductivity and integration efficiency are improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvethermal conductivityVSAvoidbonding alignment

Core Design Contradiction:

TemperatureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary formation of the first and second connection structures on their respective substrates before the bonding process. This preliminary preparation includes creating the connection structures with proper dimensions and positions, which facilitates more accurate alignment during subsequent bonding and reduces the actual precision requirements during the bonding step itself.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12132019B2Packaged multi-chip semiconductor devices and methods of fabricating same

Publication Date: 2024.10.29 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.