Multi-Chip Package Direct Bonding for Better Thermal Conduction

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in achieving high-performance and compact designs due to the limitations of traditional bump-based connections, which hinder thermal conductivity and integration efficiency.

Innovation Solution

The development of a packaged semiconductor device that connects multiple semiconductor chips via direct bonding without bumps, utilizing a structure with bond pads and insulation layers to enhance thermal conductivity and integration, allowing for smaller bond pads and improved speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If traditional bump-based connections are used to connect semiconductor chips, then the connection structure is established, but thermal conductivity is reduced and integration efficiency is hindered

Engineering Contradiction:
Improvethermal conductivityVSAvoidconnection structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent removes the bump structure from the chip connection system, extracting the problematic element that hindered thermal conductivity. By eliminating bumps and using direct bond pad contact, the connection structure is simplified while improving thermal performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces bond insulation layers as intermediaries between bond pads to enable direct bonding while maintaining electrical isolation. This mediator allows chips to be connected directly without bumps, improving thermal conductivity while preserving electrical functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Temperature

If polymer layers are used in the connection structure, then the chips are connected, but thermal conductivity is reduced due to low thermal conductivity of polymer materials

Engineering Contradiction:
Improvethermal conductivityVSAvoidmanufacturing process
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The patent changes the material parameter of the insulation layer from polymer to inorganic material. This parameter change dramatically improves thermal conductivity while the manufacturing process remains feasible through standard semiconductor fabrication techniques.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If larger bond pads are used to ensure reliable connection, then connection reliability is improved, but the package area increases and compactness is reduced

Engineering Contradiction:
Improveconnection reliabilityVSAvoidpackage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses composite material structures including inorganic insulation layers and metal bond pads with specific configurations. This composite approach enables smaller bond pad areas while maintaining reliable connections through improved material properties and structural design.

Inventive Principle:
Principle #40Composite materials

4Area of stationary object

If multiple semiconductor chips are stacked vertically to reduce layout area, then compactness is improved, but thermal management becomes more challenging

Engineering Contradiction:
Improvelayout areaVSAvoidthermal management
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The patent removes polymer layers and bump structures that impeded thermal conduction, extracting thermal resistance from the vertical stack. This enables efficient heat dissipation in multi-chip vertical configurations, allowing compact packaging without compromising thermal management.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250015026A1Packaged multi-chip semiconductor devices and methods of fabricating same
Publication Date: 2025.01.09 SAMSUNG ELECTRONICS CO LTD
  • US20250015026A1 patent drawing
  • US20250015026A1 patent drawing
  • US20250015026A1 patent drawing

AI summary

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.