Multi-Chip Display Control for Ultra-High Resolution Cost Reduction
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Solution Overview
Problem
Current display technologies face challenges in achieving ultra-high resolution displays due to the high processing workload and resource demands, which are costly and impractical for large-scale manufacturing, as ASIC chips lack the necessary capabilities and high-profile FPGA chips are expensive.
Innovation Solution
A display control device comprising multiple data generating chips and data processing chips, each configured to process image region signals, with splitting, up-scaling, and gating circuits to reduce costs while maintaining processing efficiency, allowing for segmented image processing and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-profile FPGA chip with large amount of resources is selected to achieve ultra-high resolution display, then the processing capability and resolution are improved, but the cost is very high which is disadvantageous to large quantity manufacturing
Solution Approach 1:
The patent divides the image signal processing task into multiple segments, with each data generating chip handling a specific portion of the image data. The image signal is split into multiple image region signals that are processed in parallel by separate chips, reducing the resource requirements of each individual chip while maintaining overall ultra-high resolution processing capability
Solution Approach 2:
Multiple data generating chips and data processing chips are combined to work together in a distributed architecture. The chips are connected through signal transmission lines to form a collaborative system that achieves ultra-high resolution display processing through collective effort, rather than relying on a single high-end chip
2Ease of manufacture
If ASIC chips are used for display processing, then the manufacturing cost is reduced, but they lack the capability to process large amounts of data required for ultra-high resolution display
Solution Approach 1:
The processing workload is segmented across multiple standard chips, allowing each chip to handle a manageable portion of the data while collectively achieving the required ultra-high resolution processing capacity. This segmentation enables the use of more cost-effective standard manufacturing processes
Solution Approach 2:
The patent employs standard data generating chips and data processing chips that can be used for multiple display resolutions and applications, not just ultra-high resolution. This multi-functionality allows the same chip design to serve various purposes, improving manufacturing economy through standardization
3Manufacturing precision
If the algorithm for ultra-high resolution display is implemented, then the display resolution is improved, but the processing workload and logic resources demanded are very high
Solution Approach 1:
The complex ultra-high resolution display algorithm is divided into multiple smaller processing tasks distributed across different chips. Each chip executes a portion of the algorithm on its assigned image region data, reducing the logic resource requirements of each individual chip while maintaining the overall algorithm's effectiveness
Solution Approach 2:
The patent transitions from a single-chip vertical processing architecture to a multi-chip horizontal processing architecture. By adding the dimension of spatial distribution across multiple chips, the system can handle the complex algorithm with reduced per-chip resource demands through parallel processing
Data Source
AI summary
A display control device is disclosed herein, which includes a plurality of data generating chips and a plurality of data processing chips, corresponding to one another in a one-to-one relationship. The plurality of data generating chips are configured to receive an image signal. The image signal includes a plurality of image region signals, each corresponding to a different region of an image frame. Each data generating chip is configured to receive, and to conduct data processing to, at least one image region signal to generate image region data, and to send the image region data to a corresponding data processing chip. Each data processing chip is configured to conduct image processing to the image region data from a corresponding data generating chip to generate an image output signal, and to output the image output signal. On this basis, a display method and a display apparatus are also disclosed.