Multi-Chip Semiconductor Package With Dual-Side Bonding Layout

Solution Overview

Problem

Current semiconductor package technologies face challenges in efficiently stacking and bonding multiple semiconductor chips while maintaining electrical integrity and productivity, particularly in systems-in-package (SiP) designs, where miniaturization and high performance are required.

Innovation Solution

The proposed semiconductor package employs a stacked structure with face-to-face and back-to-face bonding methods between semiconductor layers, using through-structures and bonding layers for direct electrical connections, and encapsulation to enhance signal and power integrity, and simplify manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are stacked using conventional bonding methods, then the number of chips in the package increases, but the manufacturing complexity and time increase significantly

Engineering Contradiction:

Improvenumber of semiconductor chipsVSAvoidbonding process complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the bonding process into two distinct phases: face-to-face bonding for initial chip stacking, and back-to-face bonding for subsequent chip addition. This segmentation allows different bonding orientations to be used at different stages, simplifying the overall manufacturing process while enabling multi-chip stacking.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new bonding dimension by utilizing both face-to-face (horizontal alignment) and back-to-face (vertical alignment) bonding orientations. This dimensional approach allows chips to be stacked more efficiently by changing the bonding direction, reducing process complexity compared to using only one bonding method.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If conventional stacking methods are used, then multiple chips can be packaged, but signal and power integrity deteriorate due to longer connection paths

Engineering Contradiction:

Improvenumber of stacked chipsVSAvoidsignal and power integrity

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent inverts the conventional bonding approach by implementing back-to-face bonding, where the back surface of an upper chip bonds to the front surface of a lower chip. This inversion creates shorter electrical connection paths between chips, improving signal and power integrity while maintaining the multi-chip stacked configuration.

Inventive Principle:

Principle #13The other way round (Inversion)

3Ease of manufacture

If face-to-face bonding is used for all chips, then stacking is simplified, but electrical connection paths become longer reducing performance

Engineering Contradiction:

Improvestacking process simplicityVSAvoidelectrical connection quality

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the bonding process into two distinct phases: face-to-face bonding for initial chip stacking, and back-to-face bonding for subsequent chip addition. This segmentation allows different bonding orientations to be used at different stages, simplifying the overall manufacturing process while enabling multi-chip stacking.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent inverts the conventional bonding approach by implementing back-to-face bonding, where the back surface of an upper chip bonds to the front surface of a lower chip. This inversion creates shorter electrical connection paths between chips, improving signal and power integrity while maintaining the multi-chip stacked configuration.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20240120319A1Semiconductor package

Publication Date: 2024.04.11 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a first semiconductor structure including a first semiconductor layer having a first active surface and a first circuit device thereon and a first inactive surface and first bonding layer; a second semiconductor structure on the first semiconductor structure and including a second semiconductor layer having a second active surface and second circuit device thereon and a second inactive surface, a second frontside bonding layer, and a second backside bonding layer on the second inactive surface; and a third semiconductor structure on the second semiconductor structure and including a third semiconductor layer having a third active surface including a third circuit device thereon and a third inactive surface, and a third bonding layer, wherein the first bonding layer is bonded to the second frontside bonding layer, and the third bonding layer is bonded to the second backside bonding layer.