Multi-chip Package Fan-out Signal Routing Mechanism
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Solution Overview
Problem
Conventional semiconductor packaging techniques face limitations in miniaturization, signal routing, and pad density due to the limited area of semiconductor dies, which restricts the integration density and performance of electronic components.
Innovation Solution
A multi-chip semiconductor device structure that employs a fan-out signal routing mechanism with a redistribution layer, molding compound layer, laser drilling, and under bump metallization (UBM) structures to increase pad density and signal spread, allowing for more efficient interconnects and packaging of semiconductor dies and surface-mount devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fan-in signal routing mechanism is used, then the structure is simple, but the number of input and output pads is limited due to the limited area of the die
Solution Approach 1:
The patent transitions from a two-dimensional pad layout confined to the die footprint to a three-dimensional redistribution structure that extends pads vertically and laterally through molding compound. The fan-out structure allows pads to be redistributed to an area outside the die, effectively adding spatial dimensions for signal routing.
Solution Approach 2:
The patent introduces a molding compound layer as an intermediary medium that enables the fan-out signal routing mechanism. This molding compound serves as the substrate for the redistribution layer and allows pads to be extended beyond the original die area, facilitating increased pad density without expanding the die footprint.
2Area of moving object
If die area is reduced for miniaturization, then the physical size is reduced, but the number of input and output pads is limited due to the limitation of the pitch of the input and output pads
Solution Approach 1:
The patent resolves the pitch limitation by extending the pad routing into the third dimension through the molding compound. The fan-out structure allows multiple pads to be distributed in a larger area outside the die footprint, effectively increasing pad capacity without increasing the die area or pitch.
Solution Approach 2:
The patent segments the signal routing function into two distinct areas: the die area for active components and the fan-out area in the molding compound for pad redistribution. This segmentation allows the die to remain small while the pad array can be expanded in the surrounding molding compound region.
3Quantity of substance
If fan-out signal routing mechanism is used, then the number of input and output pads can be increased, but the device complexity increases due to the need for redistribution layer and molding compound structure
Solution Approach 1:
The molding compound layer serves multiple functions simultaneously: it provides mechanical protection for the die, acts as the substrate for the fan-out structure, enables thermal management, and facilitates the redistribution of signals. This multi-functionality reduces the need for additional separate components, thereby managing complexity while achieving increased pad density.
4Productivity
If more interconnects are added to increase integration density, then the performance is improved, but the manufacturing precision requirement increases due to the complexity of interconnect structures
Solution Approach 1:
The fan-out structure provides additional lateral and vertical space for interconnect routing outside the constrained die area. This extra space in the molding compound region allows for more relaxed routing paths and larger via dimensions, thereby reducing manufacturing precision requirements while still achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased pad density and improved signal routing, facilitating higher integration density and performance while reducing physical size, power consumption, and latency in semiconductor devices.
Implementation Method 1
applying a laser drill process to the molding compound layer until two contacts of the surface-mount device are exposed
Data Source
AI summary
A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures.