Multichip FPGA Logic Drive for Low-NRE Advanced-Node Deployment
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Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly due to increased Non-Recurring Engineering (NRE) costs as semiconductor technology nodes advance, hinder innovation and adoption of advanced technology nodes.
Innovation Solution
A standardized commodity logic drive comprising multiple FPGA IC chips and non-volatile memory IC chips, allowing for field programming and configuration, which reduces NRE costs by enabling software-based innovation and application development without the need for expensive ASIC or COT chip design, and facilitates the use of advanced technology nodes like 16 nm, 10 nm, or 7 nm nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and versatility are improved, but device complexity and fabrication cost increase
Solution Approach 1:
The system is divided into two separate chips: a configuration chip that stores programming data and an FPGA chip that executes the programmed logic. This segmentation allows the FPGA chip to be optimized for logic operations while the configuration chip handles data storage, reducing the overall complexity of each individual component while maintaining field programming capability.
Solution Approach 2:
A configuration interface and control logic act as intermediaries between the configuration chip and the FPGA chip. This intermediary layer manages the complex interaction between storage and logic functions, allowing the FPGA to be programmed in the field without requiring the FPGA chip itself to contain all configuration complexity.
2Productivity
If ASIC or COT IC chips are used to expand application volume, then productivity and performance are improved, but Non-Recurring Engineering costs increase greatly
Solution Approach 1:
The system transitions from static ASIC hardware design to dynamic reconfigurable logic. The FPGA chip can be reprogrammed in the field to adapt to different applications and volume requirements, eliminating the need for expensive new mask sets when production demands change. This dynamic adaptability allows the same hardware to serve multiple production scenarios.
Solution Approach 2:
The logic functionality is changed by modifying the configuration data stored in the configuration chip rather than changing the physical chip design. This parameter change approach allows different logic implementations for different application volumes without incurring NRE costs for new mask sets, as the same FPGA hardware can be reconfigured through software.
3Productivity
If advanced technology nodes are used, then performance is improved, but Non-Recurring Engineering cost increases
Solution Approach 1:
The system separates the high-performance logic functions (implemented in advanced-node FPGA) from the configuration storage (implemented in standard-node configuration chip). This segmentation allows the performance-critical path to benefit from advanced technology nodes while the less critical configuration storage can use mature, lower-cost processes, optimizing the overall cost-performance ratio.
Data Source
AI summary
A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.