Multichip FPGA Logic Drive with Memory for Lower NRE
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Solution Overview
Problem
The transition from Field Programmable Gate Arrays (FPGA) to Application Specific ICs (ASICs) is hindered by larger chip size, higher fabrication costs, increased power consumption, and lower performance, especially at advanced technology nodes, leading to high Non-Recurring Engineering (NRE) costs that deter innovation.
Innovation Solution
A multichip package comprising standardized commodity FPGA IC chips, non-volatile memory IC chips, and cooperating IC chips, allowing for field programming and reducing NRE costs by configuring FPGA IC chips with software, enabling innovation at advanced technology nodes like 16 nm, 10 nm, 7 nm, or 5 nm, similar to the 'public innovation platform' of the 1990s.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but chip size, fabrication cost, power consumption, and performance deteriorate compared to ASIC or COT chips
Solution Approach 1:
The patent divides the logic drive system into multiple independent components: FPGA IC chips for field programming, non-volatile memory IC chips for configuration storage, and cooperating/supporting IC chips for additional functionality. This segmentation allows each component to be optimized independently, enabling the use of smaller, more efficient FPGA chips while maintaining field programming adaptability.
Solution Approach 2:
The multichip package creates a universal logic drive platform that can perform multiple functions: field programming of FPGA chips, non-volatile configuration storage, and support for various applications (AI, machine learning, IoT). This multi-functionality reduces the need for application-specific custom chips, allowing standard FPGA chips to serve diverse purposes efficiently.
2Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but fabrication cost increases compared to ASIC or COT chips
Solution Approach 1:
By segmenting the system into standardized multichip packages, the patent enables independent optimization of each chip type. This allows the use of cost-effective standard FPGA chips and memory chips manufactured through conventional processes, avoiding the high NRE costs associated with custom ASIC fabrication while maintaining field programming capabilities.
Solution Approach 2:
The patent uses non-volatile memory IC chips to store configuration data that can be copied to FPGA chips during field programming. This copying mechanism enables rapid reconfiguration without requiring expensive custom fabrication processes, as the same FPGA chip design can be reused across multiple devices with different configuration data.
3Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but power consumption increases compared to ASIC or COT chips
Solution Approach 1:
The patent uses non-volatile memory IC chips to pre-store configuration data, eliminating the need for repeated configuration operations. This preliminary action reduces power consumption by avoiding frequent programming cycles, allowing the FPGA chip to operate in a stable, low-power state once configured, while maintaining field programming adaptability when needed.
4Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but performance decreases compared to ASIC or COT chips
Solution Approach 1:
The patent segments the system to include cooperating/supporting IC chips that can handle specific processing tasks. This segmentation allows the FPGA chip to focus on flexible, reconfigurable functions while supporting chips provide optimized performance for specific operations, achieving both adaptability and high performance through coordinated multi-chip operation.
Solution Approach 2:
The multichip package creates a universal platform that can be configured for different applications (AI, machine learning, IoT) by loading appropriate configuration data into the FPGA chip. This multi-functionality allows a single standardized package to achieve application-specific performance without requiring custom ASIC fabrication for each use case.
Data Source
AI summary
A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.