Multichip FPGA Package With NVM for Lower NRE Costs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and inefficiencies of transitioning from Field Programmable Gate Arrays (FPGAs) to Application Specific ICs (ASICs) or Customer-Owned Tooling (COT) chips, particularly due to larger chip size, lower yield, higher power consumption, and increased Non-Recurring Engineering (NRE) costs, hinder innovation and adoption of advanced semiconductor technology nodes.
Innovation Solution
A multichip package comprising standardized commodity FPGA IC chips, non-volatile memory IC chips, and volatile memory IC chips, allowing for field programming and configuration, which reduces NRE costs by enabling software-based configuration and reconfiguration, thus mimicking ASIC functionality without the high costs associated with advanced technology node transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but chip size, power consumption, and fabrication cost increase compared to ASIC chips
Solution Approach 1:
The system divides the computing function into two separate components: a standardized commodity FPGA IC chip for field programming and a non-volatile memory IC chip for storing configuration data. This segmentation allows each component to be optimized independently, reducing the overall footprint while maintaining adaptability.
Solution Approach 2:
The patent moves configuration data from the FPGA chip itself to a separate non-volatile memory IC chip in the same package. This dimensional separation (spatial distribution) reduces the FPGA chip size while maintaining full programming capability through external configuration storage.
2Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but power consumption increases compared to ASIC chips
Solution Approach 1:
By separating the configuration storage function into a dedicated non-volatile memory IC chip, the FPGA chip can operate with reduced power consumption since it doesn't need to maintain large internal configuration memory, only temporary working memory during operation.
3Productivity
If advanced semiconductor technology nodes are used, then performance is improved, but Non-Recurring Engineering costs increase greatly
Solution Approach 1:
The patent creates a universal multichip package platform that can be configured for different applications through software programming of the FPGA chip. This eliminates the need for expensive custom ASIC fabrication at advanced nodes for each application, as the same physical package can be reconfigured for different functions.
Solution Approach 2:
Instead of creating custom hardware circuits for each application at advanced technology nodes, the patent uses a standardized commodity FPGA chip that can be programmatically copied and reconfigured for different applications, avoiding the high NRE costs of custom mask sets and fabrication.
4Ease of operation
If FPGA IC chips are used for field programming purposes, then ease of operation is improved, but fabrication yield decreases compared to ASIC chips
Solution Approach 1:
The patent separates the high-volume standardized FPGA chip fabrication from the application-specific configuration. The standardized chips can be manufactured with high yield using mature processes, while the specific functionality is achieved through software configuration rather than custom fabrication.
Data Source
AI summary
A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-army (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ball-grid-array (BGA) substrate.