Multi-Chip Transceiver Hybrid Cancellation for Concurrent TX/RX

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Solution Overview

Problem

Integrating multiple functions into a single large semiconductor chip leads to yield and cost disadvantages due to fixed defect density per unit area, while high-throughput communication among multiple chips in a package is desired in a power and cost-efficient manner.

Innovation Solution

A multi-chip module architecture with integrated circuit chips that include transmit and receiver circuitry, utilizing timing signal generation and synchronization to enable efficient data transfer between chips, along with optimized termination impedance and hybrid cancellation techniques to reduce power consumption and signal reflections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple functions are integrated into a single large semiconductor chip, then functionality and performance are improved, but chip yield and manufacturing cost deteriorate due to fixed defect density per unit area

Engineering Contradiction:

ImprovefunctionalityVSAvoidchip yield

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the integrated circuit system into multiple separate chips, each performing specific functions, rather than integrating all functions into a single large chip. This segmentation approach maintains the desired functionality while reducing the area of individual chips, thereby improving yield and reducing manufacturing costs.

Inventive Principle:

Principle #1Segmentation

2Reliability

If multiple chips are used in a package, then manufacturing yield and cost are improved, but communication throughput and data transfer efficiency between chips deteriorate

Engineering Contradiction:

Improvemanufacturing yieldVSAvoidcommunication throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple communication functions into a single integrated circuit chip, including transmit circuitry, receiver circuitry, timing signal generation, and data transfer pathways. This merging eliminates the need for complex inter-chip communication interfaces and enables high-speed data transfer within the chip, achieving high throughput while maintaining multi-chip package benefits.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit chip is designed with multi-functional capabilities, including both transmit and receive operations, timing signal generation, and data transfer functions. This universal design allows a single chip to perform multiple communication tasks, reducing the number of separate chips needed and improving overall system throughput.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If high-speed data transfer between chips is implemented, then communication throughput is improved, but power consumption and system complexity deteriorate

Engineering Contradiction:

Improvedata transfer rateVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the timing signal generation function from external clock sources and implements it within the integrated circuit chip itself. By generating timing signals internally, the system eliminates the need for external clock generators and complex synchronization circuits, reducing power consumption while maintaining high-speed data transfer capabilities.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The integrated circuit chip is designed to be self-sufficient by including internal timing signal generation and synchronization capabilities. The chip generates its own timing signals and performs self-synchronization, eliminating the need for external clock sources and complex equalization circuits, thereby reducing power consumption and system complexity while achieving high data transfer rates.

Inventive Principle:

Principle #25Self-service

4Reliability

If complex clock generation and equalization circuits are added, then signal integrity and data transfer reliability are improved, but device complexity and power consumption deteriorate

Engineering Contradiction:

Improvesignal integrityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12596667B2Multi-chip module including integrated circuit with receiver circuitry implementing transmit signal cancellation

Publication Date: 2026.04.07 MARVELL ASIA PTE LTD

AI summary

A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.