Multi-chip Image Sensor Packaging via 3D Vertical Stacking
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Solution Overview
Problem
Existing multi-chip packaging structures for image sensors face challenges in reducing package size, minimizing noise in image signals, and lowering manufacturing costs while maintaining effective device integration.
Innovation Solution
A multi-chip packaging structure is developed, featuring a first substrate with an image sensor device and additional integrated circuit dies, connected via conductive layers and insulating layers to a second substrate, with bond wires and vias for electrical connections, and a transparent member to reduce noise and enhance protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IC devices are assembled on the backend of the PCB with long traces, then device integration is achieved, but package size increases and noise increases
Solution Approach 1:
The patent transitions from planar 2D PCB trace routing to 3D vertical stacking with multiple substrates (first substrate, second substrate, third substrate) connected via bump members and through-substrate vias. This dimensional change allows devices to be interconnected in the vertical direction rather than requiring long horizontal traces, thereby reducing package footprint while maintaining integration capability.
2Adaptability or versatility
If IC devices are assembled on the backend of the PCB with long traces, then device integration is achieved, but noise in image signals increases
Solution Approach 1:
By routing signals vertically through stacked substrates rather than horizontally across PCB traces, the patent reduces signal path length and minimizes exposure to electromagnetic interference and crosstalk, thereby reducing noise in image signals while maintaining device integration.
Solution Approach 2:
The patent introduces intermediate substrates (first substrate, second substrate) with conductive layers and bump members that act as mediators between the image sensor device and external circuitry. These intermediates provide controlled impedance pathways and shielding, reducing noise compared to direct long PCB traces.
3Volume of moving object
If multiple devices are integrated in a compact structure, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated system into separate modular substrates (first substrate with image sensor, second substrate with processing devices, third substrate as interconnection layer) that can be manufactured independently using standard PCB and semiconductor fabrication processes, then assembled through controlled bump member attachment and via formation, thereby reducing overall manufacturing complexity compared to monolithic integration.
Data Source
AI summary
According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.