Multichip Imaging Packaging via Semiconductor Mass Interconnect
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Solution Overview
Problem
Conventional die level packaging for millimeter wave imaging systems is inefficient due to the large space required for wire bonds and potential reliability issues, especially in higher pixel count arrays, which increases the size of the imaging system and complicates the mounting process.
Innovation Solution
The use of semiconductor mass interconnect technology to form interconnections between receiver dies, reducing the space needed between dies, and the implementation of a quarter wave dielectric layer with vias to connect antennae to receiver circuits, allowing for a more compact and reliable imaging system with configurable pixel arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional die level packaging with wire bonding is used to interconnect receiver dies, then electrical connections between receiver dies and substrate can be established, but the array size increases significantly due to the large space required for wire bonds
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a semiconductor-based interconnection system. Specifically, it uses thin-film metal layers deposited directly on the substrate to create electrical pathways, eliminating the need for physical wire bonds. This substitution reduces the space required for interconnections while maintaining electrical connectivity, directly resolving the contradiction between connection reliability and array size.
Solution Approach 2:
The patent changes the interconnection method from discrete wire bonds to integrated thin-film traces. By depositing metal layers (such as aluminum or copper) in thin-film form during semiconductor fabrication processes, the interconnection structure becomes planar and integrated with the circuit board, reducing the vertical and lateral space requirements compared to elevated wire bonds.
2Productivity
If conventional die level packaging with wire bonding is used for higher pixel count arrays, then all receiver dies can be interconnected, but the number of wire bonds increases rapidly leading to increased complexity and potential failure points
Solution Approach 1:
The patent merges the interconnection function with the circuit board structure itself. Instead of treating wire bonds as separate components that must be individually managed, the thin-film metal layers are deposited as integral parts of the circuit board fabrication process. This merging reduces the number of discrete interconnection elements and simplifies the overall system, especially for high pixel count arrays where the number of connections would otherwise be extremely large.
Solution Approach 2:
The thin-film metal layers serve multiple functions simultaneously: they provide electrical interconnections between receiver dies and the substrate, act as signal routing pathways, and can serve as ground or power distribution networks. This multi-functionality reduces the overall complexity compared to dedicated wire bonds for each connection.
3Ease of manufacture
If conventional die level packaging is used, then receiver dies can be mounted to substrate, but the mounting process becomes relatively complex
Solution Approach 1:
The patent performs preliminary actions during the circuit board fabrication process itself. The thin-film interconnection layers are deposited, patterned, and prepared for receiver die attachment before the actual die mounting occurs. This preliminary preparation integrates the interconnection structure creation with the standard PCB manufacturing workflow, simplifying the subsequent die mounting process compared to conventional methods where wire bonding must be performed after die attachment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall size of the imaging system, increases reliability by minimizing wire bonds, and allows for the formation of larger pixel arrays tailored to specific applications, while also simplifying the pixel fabrication process.
Implementation Method 1
a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit
Data Source
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AI summary
A receiver chip for use in an imaging system includes a plurality of receiver dies, each of the receiver dies comprising one or more receiver circuits; a die interconnection layer located on top of the plurality of receiver dies; a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit, wherein the plurality of antennae are connected to the one or more receiver circuits through the quarter wave dielectric layer and the die interconnection layer by respective vias, such that a distance between a topmost layer of the die interconnection layer and the plurality of antennae is determined by a thickness of the quarter wave dielectric layer.