Multi-Chip Isolation Package With Laminate Transformer Heat Path
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Solution Overview
Problem
Conventional packaged semiconductor isolation (ISO) devices with reinforced isolation face limitations in thermal dissipation and size due to creepage rules, preventing them from supporting high output power applications and requiring enlarged packages.
Innovation Solution
Incorporating an isolated interposer substrate with a thermally conductive dielectric layer between top and bottom metal layers, including a laminate transformer for reinforced isolation, and using a leadframe with bondwires and mold compound encapsulation to enhance thermal dissipation and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reinforced isolation packages are used to meet creepage requirements, then electrical isolation and safety are improved, but thermal dissipation capability deteriorates and package size must be enlarged
Solution Approach 1:
The patent introduces a three-dimensional stacked architecture with multiple isolation barriers arranged vertically between IC dies, rather than relying solely on lateral creepage distance. This vertical dimension allows thermal vias to conduct heat downward through the isolation layers without compromising electrical isolation, thereby improving thermal dissipation while maintaining compact package size.
Solution Approach 2:
The patent employs thermally conductive isolation layers and thermal vias as intermediary structures that simultaneously provide electrical isolation and thermal conduction pathways. These intermediary elements allow heat to be conducted away from high-power regions through the isolation barriers without creating electrical short circuits, resolving the contradiction between isolation and thermal management.
2Reliability
If conventional reinforced isolation packages are used to meet creepage rules, then safety and electrical strength are improved, but device size increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple IC dies with isolation barriers between them, converting the lateral creepage distance requirement into a vertical isolation structure. This dimensional transition allows the package to meet electrical strength requirements through multiple thin isolation layers stacked vertically, rather than requiring a large lateral footprint, thereby reducing overall package size.
Solution Approach 2:
The patent implements a nested multi-chip module architecture where multiple IC dies are stacked vertically with isolation barriers and thermal vias integrated between them. This nesting approach allows multiple functional layers to be compactly arranged in a small volume while maintaining the required electrical isolation and thermal management capabilities.
3Reliability
If conventional reinforced isolation packages are used, then isolation performance is improved, but thermal dissipation and power handling capability deteriorate
Solution Approach 1:
The patent introduces thermally conductive isolation layers and thermal vias as intermediary structures that provide dual functionality: maintaining electrical isolation between high-voltage and low-voltage circuits while simultaneously conducting heat away from high-power regions. This resolves the contradiction by allowing heat to flow through the isolation barriers without compromising their electrical insulation properties.
Solution Approach 2:
The patent creates vertical thermal conduction pathways through the stacked isolation layers, allowing heat to be dissipated in the vertical dimension rather than being constrained to lateral dissipation. This dimensional change enables high-power handling capability while maintaining the electrical isolation performance required for reinforced isolation applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher power multi-chip ISO device packages that meet reinforced isolation requirements while maintaining compact size, supporting outputs greater than 1 W and adhering to industrial standards for safety and thermal management.
Implementation Method 1
an interposer substrate including as a thermally conductive dielectric layer between top and bottom metal layers
Implementation Method 2
the ISO device can still transfer information encoded in the desired AC signal across the isolation barrier from one IC die to the other by capacitive coupling
Implementation Method 3
by inductive coupling (transformer isolation), and the magnetic enhanced laminate transformer is known that comprises a coil 1 (with N1 turns) and a coil 2 (with N2 turns) with magnetic field enhancing magnetic cores
Data Source
AI summary
A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.