Multi-Chip Isolation Package With Interposer Cooling and Reinforced Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional packaged semiconductor isolation (ISO) devices with reinforced isolation face limitations in thermal dissipation and size due to compliance with creepage rules, preventing them from supporting high output power applications and requiring enlarged sizes to meet safety standards.
Innovation Solution
Incorporating an isolated interposer substrate with a thermally conductive dielectric layer between top and bottom metal layers, including a laminate transformer for reinforced isolation, which enhances thermal dissipation and allows for a compact design that meets safety standards while supporting higher power applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reinforced isolation device packages are designed to meet creepage rules, then safety standards are satisfied, but thermal dissipation capability is limited and device size must be enlarged
Solution Approach 1:
The patent introduces an interposer substrate that adds a vertical dimension to the isolation architecture. The interposer substrate with its dielectric layer and metal traces creates additional isolation pathways in the vertical direction, allowing the device to meet creepage requirements without increasing the horizontal footprint, thereby maintaining compact size while improving thermal dissipation through enhanced heat sinking capability.
Solution Approach 2:
The interposer substrate acts as an intermediary element between the primary isolation device and the heat sink. It provides a thermally conductive pathway that mediates heat transfer from the isolated circuits to the external heat sink, enabling efficient thermal dissipation while maintaining electrical isolation. The dielectric layer on the interposer substrate ensures that this thermal pathway does not compromise the electrical isolation requirements.
2Volume of moving object
If device size is reduced to make systems compact, then cost and space are saved, but thermal dissipation capability further deteriorates
Solution Approach 1:
By transitioning from planar thermal management to vertical thermal management through the interposer substrate, the patent enables efficient heat sinking in a compact footprint. The vertical stacking of isolation layers and thermal pathways allows heat to be conducted away from the device in the Z-direction, maintaining small X-Y footprint while achieving adequate thermal dissipation.
Solution Approach 2:
The interposer substrate employs composite construction with dielectric materials providing electrical isolation and metal traces providing thermal conduction. This composite structure enables simultaneous achievement of electrical isolation requirements and thermal management in a compact package, as the different material layers perform different functions within the same vertical space.
3Reliability
If conventional packages are designed without exposed die pad to meet isolation requirements, then reinforced isolation is achieved, but thermal dissipation and high power support are prevented
Solution Approach 1:
The interposer substrate serves as a mediator that separates the thermal management function from the electrical isolation function. It provides a dedicated thermal pathway to the heat sink that does not compromise the isolation barriers, allowing the device to achieve both reinforced isolation and high power capability through functionally independent pathways.
Solution Approach 2:
The patent segments the device architecture into distinct functional layers: isolation circuits on the primary substrate, thermal management infrastructure through the interposer substrate, and heat sinking at the base. This segmentation allows each layer to optimize its specific function without interfering with others, enabling simultaneous achievement of isolation reliability and power handling capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher power multi-chip ISO device packages that meet reinforced isolation requirements, provide efficient thermal dissipation, and comply with safety standards, allowing for compact and reliable high-power applications.
Implementation Method 1
a thermally conductive dielectric layer between top and bottom metal layers
Implementation Method 2
transfer information encoded in the desired AC signal across the isolation barrier from one IC die to the other by capacitive coupling, inductive coupling (transformer isolation)
Data Source
Figure 1
Figure 2A
Figure 2B~3
AI summary
A multi-chip isolation (ISO) device package (100) includes a leadframe including leads (114, 124), an interposer substrate (122) including a top copper layer (122a) and a bottom metal layer (122c), with a dielectric layer (122b) in-between. A first IC die (110) and a second IC die (120) include circuitry (180a, 180b) including a transmitter or a receiver, and first and second bond pads (181a, 181b) are attached top side up in the package. A laminate transformer (130) is attached to the top copper layer positioned lateral to the IC die. Bondwires (141-145) wirebond the first bond pads to first pads on the laminate transformer and to the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to leads or the lead terminals, and a mold compound (160) provides encapsulation.