Multichip Package Link CRC Detection Across Mixed Data Lanes
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Solution Overview
Problem
As computing systems become more complex, existing interconnect architectures face challenges in meeting bandwidth requirements and managing power consumption efficiently, particularly in high-performance server environments and mobile devices, where traditional solutions are either power-hungry or lack scalability.
Innovation Solution
The development of a multichip package link (MCPL) that employs a modular, protocol-agnostic physical layer and logical layer to enable high-bandwidth, low-power communication between chips, supporting multiple protocols and featuring error detection and correction mechanisms, such as cyclic redundancy check (CRC) for reliable data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If existing interconnect architectures are used to handle electrical communications, then communication capability is provided, but bandwidth requirements and power consumption cannot be efficiently managed simultaneously
Solution Approach 1:
The interconnect is divided into multiple independent lanes, each capable of carrying data simultaneously. This segmentation allows the system to scale bandwidth by activating more lanes while managing power consumption by activating only the necessary number of lanes based on data traffic requirements, resolving the contradiction between bandwidth and power consumption.
Solution Approach 2:
The interconnect architecture dynamically adjusts the number of active lanes and data rates based on real-time communication needs. This dynamic configuration enables the system to optimize the balance between bandwidth (when more lanes are active) and power consumption (when fewer lanes are active), allowing efficient management of both parameters simultaneously.
2Adaptability or versatility
If multiple protocols are supported through a single interface, then versatility is improved, but protocol-specific error detection and correction becomes more complex
Solution Approach 1:
A universal error detection and correction mechanism is implemented that works across multiple protocols (PCIe, USB 3.0, SATA, SAS) through a common framework. This universal approach maintains versatility while avoiding the complexity of implementing separate error handling systems for each protocol, as the same error detection principles apply to all supported protocols.
Solution Approach 2:
An intermediary error detection layer is introduced between the physical layer and the protocol-specific processing layers. This intermediary layer handles error detection and correction in a protocol-agnostic manner, then passes corrected data to the respective protocol handlers, thereby supporting multiple protocols without increasing overall system complexity.
3Productivity
If high-speed data transfer is implemented, then bandwidth is improved, but signal integrity and error rates deteriorate
Solution Approach 1:
A feedback mechanism is implemented where the receiving end continuously monitors signal quality and sends status information back to the transmitting end. Based on this feedback about error rates and signal integrity, the system can dynamically adjust transmission parameters such as data rate and lane configuration, allowing high-speed operation while maintaining reliability through adaptive correction.
Solution Approach 2:
Error detection and correction codes are embedded in the data transmission before errors occur. This beforehand cushioning protects against signal degradation and errors that may arise during high-speed transfer, ensuring data integrity is maintained even as transmission speed increases and signal integrity challenges arise.
Data Source
AI summary
First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.