Multichip Package Link Error Detection Across Multi-Lane Protocols
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Solution Overview
Problem
As computing systems become more complex, existing interconnect architectures face challenges in meeting bandwidth requirements and managing power consumption efficiently, particularly in high-performance server environments and mobile devices, where traditional solutions are either performance-driven or power-saving, but not both simultaneously.
Innovation Solution
The development of a multichip package link (MCPL) that employs a physical layer with regulated mid-rail termination, low power active crosstalk cancellation, circuit redundancy, per bit duty cycle correction, and deskew, along with a logical layer that supports multiple protocols and enables protocol agnostic operation, to provide a high-bandwidth, low-power, and low-latency interface for connecting devices within a package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing interconnect architectures are used to increase bandwidth, then data transfer rate improves, but power consumption increases
Solution Approach 1:
The interconnect is divided into multiple lanes, each carrying a portion of the total data traffic. This segmentation allows the system to achieve high aggregate bandwidth while enabling power management at the lane level, where inactive lanes can be powered down or put into low-power states, thus resolving the contradiction between high bandwidth and low power consumption.
Solution Approach 2:
The interconnect architecture dynamically adjusts the number of active lanes based on the data transfer requirements. When high bandwidth is needed, more lanes are activated; when bandwidth demand is lower, fewer lanes are active, reducing overall power consumption. This dynamic adaptation allows the system to optimize the balance between speed and energy usage in real-time.
2Speed
If multiple lanes are used to increase bandwidth, then data transfer rate improves, but link complexity increases
Solution Approach 1:
Multiple lanes are merged into a unified interconnect structure that operates as a single coordinated system. The lanes share common control mechanisms, error correction codes, and protocol handling, which simplifies the overall link complexity despite the increased number of physical transmission paths. This merging approach maintains manageable complexity while achieving high aggregate bandwidth.
3Reliability
If error detection mechanisms are added to improve reliability, then data integrity improves, but overhead increases
Solution Approach 1:
The error detection mechanism uses parity bits that are integrated into the data transmission format, changing the parameter structure of the data packets. By incorporating parity information efficiently into the existing lane data structure, the system achieves improved data integrity without significant overhead, as the parity bits utilize otherwise unused bits in the transmission protocol.
Data Source
AI summary
First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.