Multichip Memory Data Transfer Bypassing Host System
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Solution Overview
Problem
Conventional multichip systems experience inefficiencies in data transfer between memory chips due to reliance on a system bus, leading to prolonged data transfer times and bus occupancy, which disables other system operations.
Innovation Solution
A multichip system and method that enables direct data transfer between memory chips via a memory bus, utilizing a memory controller and local transfer mechanisms to bypass the host system, allowing for improved efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred between memory chips through the system bus in a conventional multichip system, then the data transfer can be performed with host system control, but the system bus is occupied during transfer which disables other operations and degrades system efficiency
Solution Approach 1:
The patent segments the data transfer path into two distinct pathways: (1) transfers requiring host control through the system bus, and (2) local transfers between memory chips through a dedicated memory bus. This segmentation allows critical local operations to bypass the system bus, preventing it from being occupied and maintaining overall system efficiency while preserving data transfer reliability through controlled access paths.
Solution Approach 2:
The patent introduces a memory bus as an intermediary communication channel specifically for memory chip-to-memory chip transfers. This intermediary pathway eliminates the need for memory chips to share the system bus for local operations, thereby preventing bus occupation and maintaining system efficiency, while still allowing host system mediation when necessary through the existing system bus interface.
2Reliability
If data is transferred through the system bus buffer in a conventional multichip system, then host system control is maintained, but the data transfer time is prolonged due to double loading on the system bus
Solution Approach 1:
The patent segments data transfer operations into two categories: (1) transfers requiring host intervention that use the system bus buffer, and (2) local transfers that bypass the host system entirely by using a direct memory bus connection. This segmentation eliminates the double-loading delay for local transfers while preserving host control capability for transfers that require it, thereby resolving the time-loss contradiction.
Solution Approach 2:
The patent enables preliminary establishment of direct memory bus connections between memory chips, allowing local transfers to occur immediately without waiting for host system buffer operations. By pre-configuring the memory bus pathway, the system eliminates the sequential double-loading process through the system bus buffer, significantly reducing data transfer time while maintaining host control when needed.
3Productivity
If a memory bus directly connecting memory chips is introduced, then data transfer speed is enhanced and system efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent designs the memory bus with multi-functionality, allowing it to serve both as a dedicated high-speed path for memory chip-to-memory chip transfers and as an interface to the host system through the existing system bus. This universal design enhances data transfer speed for local operations without requiring completely separate dedicated infrastructure, thereby limiting the increase in device complexity while achieving productivity improvements.
4Productivity
If local transfer mode is implemented between memory chips, then bus usage is optimized and transfer time is reduced, but the control mechanism becomes more complex
Solution Approach 1:
The patent implements self-service control mechanisms where memory chips autonomously manage their own local transfers through built-in control logic that monitors bus availability and initiates transfers without external intervention. This self-service approach optimizes bus usage efficiency by enabling immediate local transfers while avoiding the need for complex external control mechanisms, thereby resolving the contradiction between productivity and control complexity.
Data Source
AI summary
Disclosed is a multichip system and method of transferring data between memory chips in direct. The multichip system includes first and second memory chips, and a host system to control operations of the first and second memory chips. The first memory chip controls the second memory chip to transfer data to the second memory chip in response to local transfer information provided from the host system. The first memory chip controls the host system not to access the first and second memory chips while conducting a local transfer operation. According to the invention, since the data is able to be directly transferred between the memory chips without the host system, it enhances the efficiency of the multichip system and improves a data transfer speed.