Multi-Chip Module EOS/ESD Protection via Shared Die Integration
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Solution Overview
Problem
Integrated circuits (ICs) in electronic systems are vulnerable to transient electrical events like electrical overstress/electrostatic discharge (EOS/ESD), which can cause damage due to overvoltage conditions and high power dissipation, leading to potential permanent damage and increased system complexity, cost, and size when traditional protection methods are employed.
Innovation Solution
The solution involves packaging multiple IC dice within a common package, where one or more IC dice with better EOS/ESD protection capabilities share their protection elements with other IC dice, reducing the number of components and system size while enhancing overall robustness and reducing EOS/ESD-related failures, by using diodes or silicon-controlled rectifiers configured to operate in reverse-bias mode and connected through bond wires or connector elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional protection methods are employed for each IC die, then EOS/ESD protection is provided, but device complexity and system size increase
Solution Approach 1:
The patent combines multiple IC dies into a single integrated circuit package, where the packaging structure itself provides EOS/ESD protection for all included dies. This merging approach eliminates the need for separate protection circuits for each die, thereby reducing device complexity while maintaining comprehensive protection across the entire integrated circuit assembly.
2Reliability
If traditional protection methods are employed for each IC die, then EOS/ESD protection is provided, but system size increases
Solution Approach 1:
The patent merges multiple IC dies and their protection mechanisms into a single compact integrated circuit package. By integrating the protection function at the package level rather than implementing separate protection circuits for each die, the overall system size is reduced while maintaining EOS/ESD protection for all included dies.
3Reliability
If each IC die includes its own EOS/ESD protection circuits, then protection is provided, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple IC dies into a single package with centralized EOS/ESD protection, eliminating the need for duplicate protection circuits on each die. This approach reduces the total number of components, simplifies the manufacturing process, and lowers production costs while ensuring all dies within the package receive adequate protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of components and system size, increases EOS/ESD protection, and minimizes EOS/ESD-related failures, thereby enhancing the robustness of the IC assembly and reducing costs associated with stringent EOS/ESD controls.
Implementation Method 1
using diodes or silicon-controlled rectifiers configured to operate in reverse-bias mode
Implementation Method 2
electrical overstress/electrostatic discharge (EOS/ESD)
Data Source
AI summary
In one embodiment, an apparatus includes a package that encompasses at least a first integrated circuit die and a second integrated circuit die. The first integrated circuit die is attached to the package and includes one or more electrical overstress/electrostatic discharge (EOS/ESD) protection circuits. The second integrated circuit die is attached to the package and electrically coupled to the first integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by the first integrated circuit die.