Multichip Module With Segmented Conductive Carrier Parts

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Solution Overview

Problem

Conventional power semiconductor devices with copper-coated ceramic substrates are expensive to produce and face challenges in connecting chips with low impedance, leading to inefficiencies in thermal conductivity and space utilization.

Innovation Solution

A power semiconductor device with a chip carrier system comprising two electrically conductive chip carrier parts spaced apart, each housing a power transistor chip, with terminals for supply voltage potentials connected directly to the carrier parts, utilizing diffusion soldering and molding composition for insulation and mechanical protection, reducing structural height and production costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If copper-coated DCB substrate is used, then thermal conductivity is improved, but production cost increases

Engineering Contradiction:
Improvethermal conductivityVSAvoidproduction cost
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The patent replaces expensive copper-coated DCB substrates with a cost-effective alternative consisting of a ceramic substrate with a metal layer (such as aluminum or copper) that is thinner and less expensive to produce. This substitution maintains adequate thermal conductivity while significantly reducing material and production costs, making the power semiconductor device more economically viable without sacrificing essential thermal performance

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent modifies the substrate structure by changing from a thick copper-coated DCB substrate to a ceramic substrate with a thinner metal layer. This parameter change in material composition and layer thickness achieves cost reduction while maintaining the thermal conductivity function through optimized material selection and structural design

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If multiple chips are accommodated on a single substrate, then space is saved, but connecting impedance increases

Engineering Contradiction:
Improvespace utilizationVSAvoidconnecting impedance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent divides the chip carrier into multiple separately conductive parts, each directly connected to specific chips. This segmentation allows each chip to have its own dedicated electrical connection path to the terminal, reducing the impedance of connecting lines while still accommodating multiple chips in a compact arrangement on the ceramic substrate

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If chips are connected with long connecting lines, then impedance increases, but manufacturing becomes easier

Engineering Contradiction:
Improvemanufacturing easeVSAvoidimpedance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces directly conductive chip carrier parts as intermediaries between the chips and the terminal. These carrier parts serve as localized electrical connection points that minimize the length of connecting lines required, thereby reducing impedance while maintaining manufacturing simplicity through standardized mounting procedures

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables cost-effective production of power semiconductor devices with low impedance connections and enhanced thermal stability, allowing for compact and efficient integration of multiple chips in power semiconductor components.

Implementation Method 1

utilizing diffusion soldering and molding composition for insulation and mechanical protection

Methodology Applied
Scientific EffectDiffusion soldering: Diffusion Welding

Data Source

PatentUS8115294B2Multichip module with improved system carrier
Publication Date: 2012.02.14 INFINEON TECHNOLOGIES AG
  • US8115294B2 patent drawing
  • US8115294B2 patent drawing
  • US8115294B2 patent drawing

AI summary

A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conductive in each case. A first chip with a power transistor is arranged on the first chip carrier part (11) and a second chip (14) is arranged on the second chip carrier part (12). The terminal for a first potential (DC−) of a supply voltage is electrically connected to the first chip (13) via the first chip carrier part and the terminal for the second potential of a supply voltage (DC+) is electrically connected to the second chip (14) via the second chip carrier part.