Multichip Module Electrical Connection via TSVs and Redistribution
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Solution Overview
Problem
Multichip modules face issues with wire sweeping and increased fabrication costs due to long wire bonds and high terminal density, which lead to electrical shorts and broken wires during manufacturing.
Innovation Solution
The solution involves forming conductive lines and chip pads on semiconductor chips to align them at the same plane, using redistribution networks, and employing through-silicon vias (TSVs) and flip chip bonding to reduce wire bond length and angle, thereby minimizing the risks of wire sweeping and fabrication defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect terminals on upper chips to substrate, then electrical connections are established, but wire bonds become longer and form greater angles leading to wire sweeping and electrical shorts
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections using through-silicon vias (TSVs). Conductive lines are formed through the thickness of semiconductor chips, enabling connections from the upper surface to the lower surface in the vertical dimension, thereby reducing wire bond length and bonding angles
Solution Approach 2:
The patent introduces redistribution networks as intermediary conductive structures between chip terminals and wire bond connection points. These redistribution networks reroute signals to optimize wire bond paths, reducing sweeping and bonding angles while maintaining electrical connectivity
2Quantity of substance
If terminal density is increased on smaller chips, then connection density is improved, but wire bonds are more likely to break during manufacturing
Solution Approach 1:
The patent uses through-silicon vias to create vertical conductive paths through chip thickness, reducing the horizontal span of wire bonds. This dimensional change allows higher terminal density on chip surfaces while keeping wire bonds shorter and more robust
Solution Approach 2:
The patent segments the connection path into multiple sections: terminals on chip surface, conductive lines through TSVs to lower surface, and wire bonds from lower surface to substrate. This segmentation distributes mechanical stress and reduces the vulnerability of any single connection segment
3Area of moving object
If terminals are spaced closely together, then chip size is reduced, but gaps must be included between adjacent wire bond connections
Solution Approach 1:
The patent utilizes the vertical dimension through TSVs to enable closely spaced terminals to connect to substrate without requiring horizontal gaps. Wire bonds connect to the lower surface of chips where terminals are vertically aligned, allowing continuous arrays of connections without gaps between adjacent bonds
4Object-affected harmful factors
If redistribution networks are used to reduce wire bond length, then wire sweeping is minimized, but chip design complexity increases
Solution Approach 1:
The patent changes the geometric parameters of connections by forming conductive lines at different orientations and depths within the chip structure. TSVs provide vertical paths while redistribution networks create optimized horizontal paths, collectively reducing wire bond sweeping without requiring complex three-dimensional routing
Data Source
AI summary
A semiconductor chip is provided. The semiconductor chip includes a semiconductor substrate, a circuit on the substrate, an insulating layer formed on the circuit, and a plurality of electrically floating conductor lines formed on the insulating layer, at a major surface of the semiconductor chip.