Multi-Chip Package Bridge Layout for Dense Interconnects

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Solution Overview

Problem

The increasing complexity and cost of manufacturing package devices that integrate multiple active chips with high interconnection requirements due to the need for efficient interconnection structures between active chips.

Innovation Solution

A package device design that includes a substrate, conductive pillars, a redistribution layer, bridge chips, active chips, an encapsulant, and an underfill layer, where the bridge chip is coupled between the active chips and the conductive pillars, allowing for increased interconnection density and reduced manufacturing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple active chips are integrated in the same package device to meet customer requirements, then the functionality and computing power are improved, but the interconnection requirements become more complex and manufacturing cost increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidinterconnection requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a bridge chip as an intermediary component between multiple active chips. This bridge chip provides a standardized interconnection interface that simplifies the coupling between active chips, reducing the complexity of direct interconnections while enabling multiple chips to be integrated in the same package device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If multiple active chips are integrated in the same package device, then the computing power is improved, but the manufacturing cost increases

Engineering Contradiction:
Improvecomputing powerVSAvoidmanufacturing cost
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

The bridge chip serves multiple functions: it acts as an interconnection hub between active chips, provides signal routing, and enables scalable integration. This multi-functionality reduces the need for separate dedicated interconnection structures for each chip pair, thereby lowering overall manufacturing cost while supporting multiple active chips.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If the interconnection efficiency between active chips is improved by adding more interconnection structures, then the signal transmission is enhanced, but the manufacturing complexity increases

Engineering Contradiction:
Improveinterconnection efficiencyVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interconnection system is segmented into modular components: the bridge chip provides a centralized interconnection hub, while each active chip connects to the bridge through standardized interfaces. This segmentation allows for simplified manufacturing of individual components that can be assembled into a complete multi-chip package, improving interconnection efficiency without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20230282587A1Package device and manufacturing method thereof
Publication Date: 2023.09.07 POWERTECH TECHNOLOGY INC
  • US20230282587A1 patent drawing
  • US20230282587A1 patent drawing
  • US20230282587A1 patent drawing

AI summary

A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.