Multichip Lead Frame Package for Chip Isolation and Compact PCB Layout
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Solution Overview
Problem
Existing multichip packaging technologies face challenges in reducing thermal and electrical interference among semiconductor chips, leading to malfunctions and increased package size, and individual chip packaging increases PCB size and soldering complexity.
Innovation Solution
A multichip package design featuring semiconductor chips mounted on individual lead frame pads with fixed frames and bonding wires, where the lead frames connected to MOSFET chips have a stepped portion to minimize interference and reduce package size, and the use of Ag epoxy for chip bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are mounted on a single lead frame pad, then packaging density is improved, but thermal and electrical interference occurs among neighboring chips
Solution Approach 1:
The lead frame pad is divided into multiple independent regions, with each region dedicated to mounting a single semiconductor chip. This segmentation isolates the thermal and electrical fields of adjacent chips, preventing interference while maintaining high packaging density through efficient use of the lead frame pad area.
Solution Approach 2:
Different regions of the lead frame pad are designed with locally optimized properties - each region is configured to accommodate specific chip types with appropriate electrical connection patterns and thermal dissipation characteristics, allowing dense packaging without uniform interference across all chip locations.
2Object-affected harmful factors
If individual packages are mounted on PCBs, then chip isolation is improved, but PCB size and soldering complexity increase
Solution Approach 1:
Multiple semiconductor chips that would traditionally require separate packages are merged onto a single lead frame pad in an integrated arrangement. The lead frame pad structure provides both mechanical support and electrical interconnection for multiple chips simultaneously, achieving chip isolation through structural design rather than physical separation into individual packages, thereby reducing PCB footprint.
3Ease of manufacture
If individual packages with PCBs are used, then manufacturing flexibility is improved, but the number of soldering operations and assembly steps increases
Solution Approach 1:
Multiple semiconductor chips are pre-assembled and electrically interconnected on the lead frame pad before the final packaging stage. This preliminary assembly integrates multiple components into a single unit that requires only one soldering operation to mount on the PCB, eliminating the need for multiple separate soldering operations and assembly steps while maintaining manufacturing flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes thermal and electrical interference among chips, reduces package size, and simplifies the manufacturing process by allowing more chips to be integrated on a smaller PCB without the need for additional heat sinks, while preventing moisture ingress and delamination.
Implementation Method 1
lead frames connected to the semiconductor chips by a bonding wire
Implementation Method 2
the use of Ag epoxy for chip bonding
Data Source
AI summary
A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.