Multi-Chip Package Conductive Layer for Wire Bonding
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Solution Overview
Problem
In multi-chip packages, the increased complexity of wire bonding between multiple chips and passive elements leads to issues like wire entanglement, short-circuiting, and reduced yield rates due to dense wiring layouts, making it difficult to integrate multiple chips efficiently.
Innovation Solution
The use of a conductive layer as a transfer terminal to connect wires between chips and the carrier, avoiding direct entanglement and sweeping by assembling contacts on the conductive layer first and then transferring them to a target region on the carrier, such as a grounding or power region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips and passive elements are integrated together to achieve high density, then the integration density is improved, but wire bonding becomes more difficult and wire entanglement occurs
Solution Approach 1:
The patent introduces a conductive layer as an intermediary transfer terminal between chips and the lead frame. This conductive layer receives wire bonds from chip pads and transfers electrical connections to the lead frame, acting as a mediator that simplifies the wire bonding process by providing a dedicated bonding surface and reducing wire entanglement in high-density configurations.
Solution Approach 2:
The patent adds a vertical dimension to the wiring architecture by stacking chips above each other with conductive layers between them. This three-dimensional arrangement allows wires to be routed vertically through conductive layers rather than horizontally across the lead frame, reducing wire entanglement and enabling higher integration density.
2Adaptability or versatility
If wire layout is intensified to connect multiple chips, then the connectivity is improved, but wire short-circuiting and wire sweeping occur
Solution Approach 1:
The conductive layer serves as an intermediary that separates wire bonding operations into distinct stages: first bonding wires from chip pads to the conductive layer, then bonding from the conductive layer to the lead frame. This separation reduces the risk of wire short-circuiting and sweeping by providing physical isolation between wire groups.
Solution Approach 2:
The wiring path is segmented into multiple independent stages using conductive layers as intermediate transfer terminals. Each conductive layer handles specific wire connections locally, segmenting the overall wiring complexity and reducing the probability of short-circuits by isolating wire groups in different vertical planes.
3Device complexity
If direct wire bonding between chips and lead frame is used, then the connection path is simplified, but wire entanglement and bonding difficulty increase
Solution Approach 1:
The conductive layer acts as a mediator that simplifies the bonding process by providing a dedicated, accessible surface for wire bonding. Rather than attempting complex long-range wire bonds directly between distant chip pads and lead frame terminals, the conductive layer breaks this into two simpler bonding operations with better geometric alignment.
Solution Approach 2:
The conductive layer is pre-positioned between the chip and lead frame before final assembly, establishing a predetermined wire bonding path. This preliminary arrangement of the conductive transfer terminal allows wires to be bonded in an optimized configuration before the complete assembly is finalized, making the bonding process more manageable.
Data Source
AI summary
A multi-chip package including a carrier, a first chip, a second chip and a first conductive layer is provided. The first chip is disposed on the carrier and is electrically connected to the carrier through at least one first wire. The second chip is disposed on the first chip and is electrically connected to the first chip through at least one second wire. The first conductive layer is disposed on the second chip and is electrically connected to the first chip or the second chip through at least one third wire. The first conductive layer is electrically connected to the carrier through the at least one fourth wire.


