Multi-Chip Package Layout for High-Density Die-to-Die Interconnects
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Solution Overview
Problem
The challenge lies in manufacturing package substrates large enough to accommodate multiple integrated circuit devices while minimizing exposure to potentially harmful processes.
Innovation Solution
The implementation of multi-chip packages with high density interconnects, which utilize panel-level processing to achieve interconnect densities greater than 100 IO per mm, enabling efficient connectivity for high bandwidth memory solutions and reducing the number of process steps post-die placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package substrates are made large enough to accommodate multiple integrated circuit devices, then the number of devices per package increases, but the manufacturing complexity and exposure to harmful processes increases
Solution Approach 1:
The manufacturing process is divided into pre-attachment processing (conductive interconnect formation on substrate) and post-attachment processing (die bonding and wire bonding). This segmentation allows complex interconnect structures to be formed on the substrate before die attachment, reducing the complexity of post-attachment processes and minimizing harmful exposures to finished devices.
Solution Approach 2:
Conductive interconnects are formed on the substrate surface and within organic dielectric layers before the integrated circuit dies are attached. This preliminary formation of complex interconnect structures eliminates the need for subsequent drilling, plating, and routing operations that would expose finished devices to harmful chemical and thermal processes.
2Ease of operation
If traditional wiring methods are used, then device connectivity is achieved, but printed circuit board space is excessively consumed
Solution Approach 1:
The patent transitions from two-dimensional planar routing on traditional PCBs to three-dimensional vertical interconnects through organic dielectric layers. Conductive vias and traces are formed in multiple layers above and below the substrate surface, enabling high-density interconnects that dramatically reduce the footprint on the printed circuit board while maintaining full device connectivity.
Solution Approach 2:
Multiple conductive interconnect layers are nested within organic dielectric layers, creating a multi-layered interconnect structure. This nesting allows numerous signal paths to be packed into a compact volume, achieving high interconnect density without increasing the lateral footprint on the printed circuit board.
3Manufacturing precision
If wafer-level processing is used for high density interconnects, then interconnect density increases, but yield loss increases due to reticle-size limitations
Solution Approach 1:
Instead of forming high-density interconnects at the wafer level before die separation (which is constrained by reticle size), the patent inverts the approach by forming the interconnects on the packaged substrate after die attachment. This allows the use of large substrate areas without reticle limitations, achieving high interconnect density while maintaining full die yield.
Data Source
AI summary
An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.