Multi-chip Package Fan-out Signal Routing
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Solution Overview
Problem
Conventional semiconductor packaging techniques face limitations in miniaturization, signal routing, and pad density due to the limited area of semiconductor dies, particularly in fan-in configurations, which restricts the number of input and output pads and hinders further integration and performance enhancements.
Innovation Solution
A multi-chip semiconductor device employing a fan-out signal routing mechanism with a redistribution layer and a molding compound layer that embeds semiconductor dies and surface-mount devices, along with metal pillars and interconnect structures, allows for increased pad density and signal redistribution beyond the die area, enabling more efficient packaging and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fan-in signal routing mechanism is used, then the semiconductor device structure is simple, but the number of input and output pads is limited due to the limited die area
Solution Approach 1:
The patent transitions from a two-dimensional pad layout confined to the die surface to a three-dimensional structure by extending the signal routing into the molding compound layer. Redistribution layers are formed at different depths within the molding compound, allowing pads to be redistributed in the vertical dimension as well as horizontally, thereby increasing the effective pad area beyond the die footprint.
Solution Approach 2:
The molding compound layer serves as an intermediary medium that enables signal redistribution. By forming redistribution layers within the molding compound, the patent creates an intermediate routing plane that decouples the pad layout from the die area constraints, allowing signals to be routed to locations outside the original die boundaries.
2Quantity of substance
If fan-out signal routing mechanism is used, then the number of input and output pads can be increased, but the device complexity increases due to redistribution layers and extended interconnects
Solution Approach 1:
The patent merges the redistribution function with the existing molding compound structure. Instead of adding separate redistribution layers outside the molding compound, the invention integrates the routing functionality directly within the molding material, combining the protective encapsulation function with the signal redistribution function in a single integrated structure.
Solution Approach 2:
The molding compound layer is given multiple functions: it serves both as the traditional protective encapsulation material and as the medium for signal redistribution. The redistribution layers formed within the molding compound perform dual roles of electrical interconnection and structural support, reducing the need for additional dedicated routing structures.
3Quantity of substance
If the die area is increased to accommodate more pads, then the number of pads can be increased, but the miniaturization goal is compromised
Solution Approach 1:
The patent resolves the area constraint by utilizing the vertical dimension within the molding compound layer. Redistribution layers are formed at different depths (e.g., first redistribution layer at a first depth, second redistribution layer at a second depth), effectively creating a three-dimensional routing architecture that increases pad capacity without expanding the horizontal device footprint.
Solution Approach 2:
The invention implements a nested structure where multiple redistribution layers are positioned at different depths within the molding compound layer. This nested arrangement of conductive layers allows signals to be routed through multiple hierarchical levels, maximizing the use of available space and enabling high-density interconnection within a compact footprint.
Data Source
AI summary
A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.