Multi-Chip Semiconductor Package Layout for Heat Dissipation
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and efficient heat dissipation while maintaining a small form factor, which is essential for miniaturization and weight reduction in portable devices.
Innovation Solution
A semiconductor package design featuring a first substrate with a cavity, multiple chips, and a redistribution structure that includes bridge chips for electrical connections, along with heat dissipation members to manage thermal issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are integrated in a compact arrangement to achieve high integration, then the integration capability is improved, but the heat dissipation efficiency deteriorates
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional vertical stacking, placing chips at different heights (first chip on substrate, second chip on first chip, third chip on redistribution structure) to achieve high integration while maintaining heat dissipation pathways in the vertical dimension
Solution Approach 2:
The patent divides the package into multiple independent chip modules (first chip, second chip, third chip) connected through redistribution structures, allowing each chip to be independently cooled while maintaining close integration, thus resolving the heat dissipation issue in high-integration configurations
2Volume of moving object
If chip size and package volume are reduced to achieve miniaturization, then the volume is improved, but the heat dissipation capability deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal footprint of the package while maintaining adequate heat dissipation volume through the vertical dimension, achieving miniaturization without sacrificing thermal management capability
Solution Approach 2:
The patent embeds smaller chips and redistribution structures within and between larger structural elements (substrate, molding compound, heat dissipation members), creating a nested configuration that maximizes space utilization for miniaturization while preserving heat dissipation pathways
3Productivity
If complex redistribution structures are added to connect multiple chips, then the integration is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple redistribution functions into unified redistribution structures that simultaneously connect multiple chips (first chip, second chip, third chip) to the substrate, reducing the number of separate connection structures needed and simplifying the overall device complexity
Data Source
AI summary
A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.