Multi-chip Package Interconnect Bridge with Discrete Redistribution Layers
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Solution Overview
Problem
Conventional semiconductor packaging technologies, such as ceramic-based and organic laminate substrates, are limited in achieving high-density I/O flip-chip connections and die-to-die interconnections due to constraints on contact pad pitch, line width, and line spacing, which hinders the development of high-density packaging for increasingly functional and compact IC chips.
Innovation Solution
The implementation of multi-chip package structures comprising interconnect bridge devices and discrete redistribution layers, which provide high I/O interconnect density and bandwidth through fine-pitch wiring and lateral power distribution, enabling efficient connections between chip packages and overcoming the limitations of traditional substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ceramic-based or organic laminate substrates are used for MCM packaging, then the package structure can be constructed with standard fabrication processes, but the contact pad pitch, line width, and line spacing are limited and cannot achieve high-density I/O flip-chip connections
Solution Approach 1:
The package structure is divided into separate functional components: the substrate provides mechanical support and basic routing, while discrete redistribution layers (RDLs) are added on top to provide the fine-pitch interconnects needed for high-density packaging. This segmentation allows each component to be optimized independently - the substrate for ease of manufacture and the RDLs for manufacturing precision.
Solution Approach 2:
Instead of attempting to achieve fine-pitch interconnects within the planar substrate layer, the solution moves to another dimension by stacking redistribution layers vertically on top of the substrate. This vertical stacking enables high-density interconnects without compromising the substrate's fabrication capabilities.
2Manufacturing precision
If silicon interposers with TSVs are used to achieve high wiring density, then I/O redistribution and die-to-die communication are improved, but the cost and fabrication complexity increase significantly
Solution Approach 1:
The patent uses discrete redistribution layers made from standard organic laminate materials instead of expensive silicon interposers. These RDLs can be fabricated using conventional PCB processes, making them much cheaper and simpler to manufacture while achieving the same functional goal of high-density interconnects.
Solution Approach 2:
The discrete redistribution layers act as intermediary structures between the substrate and the IC chips. They provide the fine-pitch routing needed for high-density packaging without requiring the complex TSV technology of silicon interposers, thus mediating between the simple substrate and the high-performance requirements.
3Quantity of substance
If finer pitch wiring is implemented to increase I/O density, then more I/O connections can be made in a smaller area, but the line width and line spacing design rules become more restrictive
Solution Approach 1:
The interconnect structure is segmented into two parts: the substrate handles power distribution and coarse routing with relaxed design rules, while the discrete redistribution layers handle the fine-pitch signal routing. This segmentation allows each layer to be optimized for its specific function without being constrained by the other's design rules.
Data Source
AI summary
Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.