Multi-Chip Package Assembly With Carrier-Mounted Interconnect Bridges
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Solution Overview
Problem
Conventional multi-chip interconnection technologies, such as EMIB, require complex and expensive packaging processes, making them costly and difficult to implement for high-efficiency and high-density chip interconnections.
Innovation Solution
A method for forming chip packages that involves mounting chipsets with interconnection devices on a carrier, forming a molded encapsulation layer, exposing bumps, and forming secondary bumps on the encapsulation layer, allowing for simpler and less costly manufacturing without embedding interconnect devices in a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional EMIB technology is used to embed silicon bridges in substrate for chip interconnection, then interconnection density and efficiency are improved, but packaging process complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent extracts the interconnection function from the substrate embedding approach and relocates it to standalone interconnection devices that are mounted on the carrier. This separates the interconnection functionality from the substrate, allowing chips to be interconnected through these discrete devices rather than through embedded silicon bridges, thereby simplifying the overall packaging process while maintaining high interconnection density
Solution Approach 2:
The patent segments the interconnection system into independent modular components: chips with bumps, standalone interconnection devices, and a carrier. This segmentation allows each component to be optimized and manufactured separately, then assembled together, reducing packaging process complexity compared to the integrated substrate embedding approach
2Productivity
If conventional EMIB technology is used to embed silicon bridges in substrate for chip interconnection, then interconnection efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs cost-effective interconnection devices that can be manufactured using standard semiconductor fabrication processes and mounted on the carrier. These interconnection devices serve as affordable alternatives to expensive embedded silicon bridge structures, achieving the required interconnection efficiency without the high manufacturing costs associated with substrate embedding
Solution Approach 2:
The patent performs preliminary mounting of interconnection devices on the carrier before final chip assembly. This preliminary action allows for optimized manufacturing workflows where interconnection devices are prepared and positioned in advance, facilitating more efficient and cost-effective assembly processes compared to post-substrate embedding operations
Data Source
AI summary
The present application provides a method for forming a chip package and a chip package. The method comprises mounting at least one chipset including at least first and second chips on a carrier with front surface of the chips face away from the carrier; attaching an interconnection device to the front surfaces of the first and second chips to enable electrically connections between the chips; forming a molded encapsulation layer whereby the first chip, the second chip and the interconnection device are embedded or partially embedded in the molded encapsulation layer; thinning one side of the molded encapsulation layer away from the carrier to expose first bumps on the first and second chips; forming second bumps on a surface of one side of the molded encapsulation layer where the first bumps are exposed; and removing the carrier. Thus, a flexible, efficient and low-cost packaging scheme is provided for multi-chip connection.