Multi-Chip Package Layout for Mismatched Die I/O Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating semiconductor dies with different I/O pad locations, which hinders the vertical stacking of signal processing dies over memory dies in 3D integrated circuit (3DIC) packages, leading to larger package sizes and potential warpage issues.
Innovation Solution
A redistribution structure is formed over the semiconductor die to re-route electrical connections from original I/O pad locations to new locations within the die, allowing for the integration of dies with varying I/O pad configurations, and conductive pillars are used to connect these dies, enabling efficient stacking and reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor dies are vertically stacked to reduce package size, then the physical size is reduced, but integration of dies with different I/O pad locations becomes difficult
Solution Approach 1:
A redistribution structure acts as an intermediary between the first die and the second die, re-routing electrical connections from the original I/O pad locations to new locations that enable vertical stacking. This mediator allows dies with different I/O pad configurations to be integrated together by translating their connection interfaces.
Solution Approach 2:
The invention transitions from a two-dimensional planar arrangement of I/O pads to a three-dimensional stacked configuration by introducing vertical conductive pillars and redistribution structures, enabling integration along the vertical dimension rather than only in the horizontal plane.
2Adaptability or versatility
If conventional packaging techniques are used, then integration of different die configurations is easier, but package size increases
Solution Approach 1:
The invention moves from conventional two-dimensional packaging to three-dimensional stacking by introducing vertical conductive pillars and redistribution structures, enabling multiple dies to be integrated in the vertical dimension, thereby reducing the horizontal footprint and overall package size.
3Ease of manufacture
If I/O pad locations are kept original, then manufacturing is simpler, but vertical stacking of signal processing dies over memory dies is hindered
Solution Approach 1:
The redistribution structure is formed in advance during the manufacturing process, re-routing electrical connections before the vertical stacking assembly takes place. This preliminary action prepares the die interfaces to accommodate vertical stacking while maintaining manufacturing efficiency through integrated process steps.
Data Source
AI summary
A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.