Multi-Chip Package Lead Frame Layout for Low-Resistance Connections

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Solution Overview

Problem

Conventional multi-chip package devices face issues with electrical characteristics due to thin bonding wires having high resistance and soldering joints that can fall off during encapsulation, leading to potential short circuits and damage from stress buildup during lead bending.

Innovation Solution

A method involving a lead frame unit with a metal layer that covers the transistor chip and connects to source electrode pads, allowing for external electrical connection without soldering joints, and bending the metal layer's leg part after encapsulation to reduce stress on the encapsulation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding wires are used to electrically connect chips to leads, then electrical connection is achieved, but electrical resistance increases and reliability decreases due to thin wire diameter and soldering joint failures

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidelectrical resistance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the bonding wire component from the electrical connection path and replaces it with a direct lead frame-to-chip electrode connection. The lead frame's base seat serves as the primary electrical connection element, eliminating the thin bonding wire that caused high resistance and reliability issues.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The lead frame's base seat performs multiple functions: it provides mechanical support for the chips, serves as the primary electrical connection element with low resistance, and acts as a mounting platform. This multi-functional design replaces the separate bonding wire and soldering joint components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If leads are bent to be coplanar for external connection, then external electrical connection is enabled, but stress buildup occurs at bending points causing damage during encapsulation

Engineering Contradiction:
Improveexternal electrical connectionVSAvoidstructural integrity at bending points
Core Design Contradiction:
Ease of operationVSStrength

Solution Approach 1:

The leads are pre-formed into the coplanar configuration during lead frame manufacturing, before chip mounting and encapsulation. This preliminary shaping allows the leads to be in the correct position for external connections while distributing stress away from critical bending points during subsequent processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The base seat serves as an intermediary element between the leads and the chips. It provides a stable mounting surface that distributes mechanical stress, preventing stress concentration at lead bending points while enabling external electrical connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple chips are stacked and packaged to improve functionality, then device capability increases, but device size increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidpackage size
Core Design Contradiction:
Adaptability or versatilityVSVolume of moving object

Solution Approach 1:

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Multiple chips are arranged vertically on the lead frame's base seat, utilizing the vertical dimension to increase functionality while maintaining a compact footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple chips are nested vertically on the same lead frame base seat, with each chip stacked above the previous one. This nesting arrangement allows multiple functional components to be integrated in a compact vertical stack rather than spreading them out horizontally.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250022721A1Method of making a multi-chip package device
Publication Date: 2025.01.16 FORCE MOS TECH CO LTD
  • US20250022721A1 patent drawing
  • US20250022721A1 patent drawing
  • US20250022721A1 patent drawing

AI summary

A method for making a multi-chip package device includes: providing a lead frame unit having a plurality of lead frames, each of the lead frames having a base seat that has an upper surface and a bottom surface, and a plurality of leads; electrically attaching a transistor chip onto the base seat, the transistor chip having a plurality of electrode pads; attaching a circuit control chip to the base seat; covering the transistor chip with a main conducting part, and electrically connecting the main conducting part with at least one of the source electrode pads; electrically connecting the circuit control chip to another source electrode pad; encapsulating the transistor chip and the circuit control chip to expose a leg part; and bending the leg part that is exposed to form a planar conducting portion having a bottom surface coplanar with the bottom surface of the base seat.