Multi-Chip Package Metallic Frame Layout for Low-Resistance Connections
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Solution Overview
Problem
Conventional multi-chip package devices face issues with electrical characteristics due to thin bonding wires having high resistance and soldering joints prone to failure, leading to potential short circuits and damage from stress buildup during encapsulation.
Innovation Solution
A multi-chip package device design featuring a lead frame with a metallic frame and encapsulation layer, where the metallic frame's conducting legs provide external electrical connections, eliminating the need for soldering joints and reducing stress-induced damage by bending the legs outside the encapsulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to electrically connect chips to leads, then electrical connection is achieved, but electrical resistance increases and reliability decreases
Solution Approach 1:
The patent removes bonding wires from the electrical connection path entirely. Instead, conducting legs with large contact areas directly connect chip electrodes to lead frame leads, eliminating the thin bonding wire interface that caused high resistance and reliability issues.
Solution Approach 2:
The patent changes the connection geometry by using conducting legs with large contact areas instead of thin bonding wires. This parameter change from small wire diameter to large leg contact area dramatically reduces electrical resistance while improving mechanical strength and reliability.
2Reliability
If soldering joints are used to connect bonding wires to leads, then electrical connection is established, but soldering joints are prone to falling off during encapsulation causing short circuits
Solution Approach 1:
The patent eliminates soldering joints from the connection process. Conducting legs make direct mechanical and electrical contact with chip electrodes and lead frame leads without requiring solder, removing the failure point where solder joints would detach during encapsulation stress.
Solution Approach 2:
The patent replaces the soldering process (thermal-mechanical joining) with direct mechanical contact through conducting legs. This substitution eliminates the need for soldering joints that are vulnerable to stress-induced detachment during encapsulation.
3Ease of operation
If leads are bent to be coplanar for external connection, then external electrical connection is enabled, but stress buildup at bending points causes damage to encapsulation layer
Solution Approach 1:
The patent removes leads from the encapsulation area entirely. Conducting legs extend from the chip through the encapsulation layer to provide external connections, eliminating the need to bend leads within or at the edges of the encapsulation material where stress concentration would cause damage.
Solution Approach 2:
The patent changes the spatial arrangement by extending conducting legs in the vertical dimension through the encapsulation layer rather than bending leads in the horizontal plane at the encapsulation boundary. This dimensional change moves bending points outside the encapsulation stress zone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical performance by reducing resistance and preventing soldering joint failures, while minimizing stress-induced damage to the encapsulation layer, thus improving the reliability and durability of the multi-chip package device.
Implementation Method 1
The conducting leg is integrally formed with the main conducting part, and extends from the main conducting part for external electrical connection
Implementation Method 2
the point of bending on each of the leads will be either within or on the edge of the encapsulating material, the conventional multi-chip package device is easily damaged by the stress buildup from bending of the leads
Data Source
AI summary
A multi-chip package device includes a lead frame, a transistor chip, a metallic frame, a circuit control chip, and an encapsulation layer. The lead frame has a base seat, and a plurality of leads. The transistor chip is disposed on the base seat, and includes a plurality of source electrode pads, a gate electrode and a drain electrode. The metallic frame has a main conducting part and a conducting leg having a first conducting section and a second conducting section. The circuit control chip is disposed on the base seat and electrically connected to the transistor chip and the leads. The encapsulation layer envelops the lead frame, the transistor chip, the main conducting part, the first conducting section, and the circuit control chip to expose the second conducting section of the conducting leg.