Multichip Package Noise Reduction via Chip Thickness Variation
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Solution Overview
Problem
Multichip packages with RF analog and digital circuit areas experience noise propagation issues due to the proximity of digital circuit areas to RF analog circuit areas, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor integrated circuit device design where the first semiconductor chip with an RF analog circuit area is made thinner than the second semiconductor chip with a digital circuit area, utilizing an organic multilayer wiring board and bonding wires to interconnect them, with specific structural features like guard bands and guard rings to prevent noise propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If digital circuit areas are placed close to RF analog circuit areas to increase integration density, then productivity and area utilization are improved, but noise propagation from digital to RF analog circuits increases
Solution Approach 1:
The patent applies local quality by creating a thickness difference between the first semiconductor chip (RF analog circuit area) and the second semiconductor chip (digital circuit area). The first chip is made thinner than the second chip, so that the chip thickness is not uniform across different functional areas. This local variation in thickness increases parasitic inductance and resistance in the noise path from digital to RF analog circuits, thereby reducing noise propagation while maintaining close proximity for high area utilization.
2Object-affected harmful factors
If the first semiconductor chip is made thinner to reduce noise path coupling, then noise propagation is reduced, but mechanical strength may be compromised
Solution Approach 1:
The patent implements local quality by making the first semiconductor chip (containing RF analog circuit area) thinner than the second semiconductor chip (containing digital circuit area). This localized thickness reduction is applied only where needed for noise reduction, while the overall package structure maintains mechanical strength through the thicker second chip and proper packaging design.
Solution Approach 2:
The patent applies asymmetry by creating an intentional thickness difference between the two semiconductor chips. The first chip is designed with a smaller thickness than the second chip, creating an asymmetric structure that increases parasitic inductance in the noise path while maintaining overall package integrity and mechanical strength.
3Ease of manufacture
If bonding wires are used to interconnect chips, then ease of manufacture is improved, but wire short-circuits may occur due to proximity
Solution Approach 1:
The patent applies parameter changes by modifying the thickness parameter of the first semiconductor chip. By making the first chip thinner than the second chip, the vertical distance between bonding wires and the chip surface is reduced, which changes the bonding parameters and reduces the risk of wire short-circuits while maintaining ease of manufacture through standard bonding wire processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces noise propagation from digital circuit areas to RF analog circuit areas by increasing parasitic inductance and resistance in the noise path, preventing wire short-circuits and ensuring reliable signal transmission.
Implementation Method 1
increasing parasitic inductance and resistance in the noise path
Implementation Method 2
increasing parasitic inductance and resistance in the noise path
Implementation Method 3
a plurality of bonding wires which interconnect between a plurality of terminals provided over respective surfaces of the first and second semiconductor chips
Data Source
AI summary
The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip.