Multi-Chip Package Interconnect Layout for Panel-Level Assembly

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Solution Overview

Problem

The challenge lies in manufacturing multi-chip packages with high density interconnects that can accommodate multiple integrated circuit devices while minimizing exposure to harmful processes, which is difficult due to the limitations of existing wafer-level processing methods.

Innovation Solution

The solution involves panel-level processing, which reduces the number of post-placement process steps and allows for high density interconnects between two or more dies with an interconnect density of greater than 100 IO per mm, utilizing organic dielectric layers and copper interconnects to couple fine pitch contacts, and enabling the use of full reticle dies in a System on Package configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wafer-level processing methods are used to manufacture multi-chip packages, then manufacturing capability is provided, but the number of harmful process exposures increases and manufacturing complexity increases

Engineering Contradiction:

Improvemanufacturing capabilityVSAvoidharmful process exposures

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent segments the manufacturing process into panel-level processing followed by post-placement processes. The high density interconnect substrate is manufactured separately at panel level using fewer harmful processes, then dies are placed and connected using bump bonding and reflow processes. This segmentation allows the substrate to avoid exposure to multiple harmful processes while still achieving high density interconnect functionality.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If wafer-level processing methods are used to manufacture multi-chip packages, then manufacturing capability is provided, but device complexity increases

Engineering Contradiction:

Improvemanufacturing capabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The manufacturing process is divided into distinct segments: panel-level substrate fabrication, die placement, bump bonding, and reflow processing. Each segment can be optimized independently, reducing overall process complexity compared to monolithic wafer-level processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The high density interconnect substrate is fabricated in advance at panel level using organic dielectric layers and copper interconnects before die placement. This preliminary action simplifies subsequent assembly steps by providing a pre-configured interconnect structure that requires fewer post-placement process steps.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If high density interconnects with interconnect density greater than 100 IO per mm are implemented, then connectivity efficiency is improved, but manufacturing difficulty increases

Engineering Contradiction:

Improveconnectivity efficiencyVSAvoidmanufacturing difficulty

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent achieves high density interconnects (>100 IO per mm) by changing material parameters: using organic dielectric layers with appropriate dielectric constants and copper interconnects with controlled thickness and conductivity. These parameter changes enable high density connectivity while maintaining manufacturability through panel-level processing.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The high density interconnect structure uses composite materials including organic dielectric layers combined with copper interconnects. This composite approach enables the achievement of high interconnect density while maintaining ease of manufacture through panel-level processing techniques.

Inventive Principle:

Principle #40Composite materials

4Object-affected harmful factors

If panel-level processing is used instead of wafer-level processing, then the number of harmful processes is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improveharmful process exposuresVSAvoidprocessing precision

Core Design Contradiction:

Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The high density interconnect substrate is fabricated in advance at panel level with precise copper interconnect patterns and organic dielectric layer structures before die placement. This preliminary precision fabrication reduces the need for subsequent precision processes, thereby reducing harmful process exposures while maintaining manufacturing precision.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11908802B2Multi-chip package with high density interconnects

Publication Date: 2024.02.20 INTEL CORP

AI summary

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.