Multi-Chip Package with Frontside and Backside Redistribution Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current packaging technologies face challenges in achieving high functional density and integration density while maintaining low costs and high performance, particularly in multi-chip packages where efficient electrical connections and redistribution layers are required.
Innovation Solution
The implementation of a multi-chip package structure with frontside and backside redistribution layers (RDLs), conductive pillars, and conductive vias, along with a molding compound, allows for efficient electrical connections and increased functional density by redistributing I/O pads and integrating multiple chips within a single package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fan-out packages are formed to redistribute I/O pads over a greater area, then the number of I/O pads packed on the surfaces of packaged dies is increased, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The package structure is divided into multiple segments including frontside RDL, backside RDL, conductive pillars, and molding compound layers. Each segment performs a specific function in the signal redistribution path, allowing complex I/O pad redistribution to be achieved through modular construction rather than a single complex layer
Solution Approach 2:
The patent transitions from planar (2D) RDL redistribution to three-dimensional (3D) redistribution by stacking multiple RDL layers at different heights and using conductive pillars for vertical interconnections. This vertical dimension enables denser I/O pad packing by utilizing space in the Z-direction rather than only expanding the footprint area
2Quantity of substance
If multiple chips are integrated within a single package to increase functional density, then high-performance multi-chip packages are achieved, but the manufacturing process complexity increases
Solution Approach 1:
The conductive pillars and vias are formed and positioned before the chips are mounted in the final assembly. This preliminary formation of interconnection structures allows for more precise alignment and reduces the complexity of subsequent chip mounting operations, as the electrical connection pathways are already established
Solution Approach 2:
The RDL structure serves multiple functions simultaneously: it provides electrical interconnection between chips, enables signal redistribution to increased I/O pads, and provides mechanical support and alignment features for chip mounting. This multi-functionality reduces the need for separate specialized structures, simplifying the overall manufacturing process
3Reliability
If frontside and backside redistribution layers are implemented to enhance electrical connectivity, then high-performance packages are achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The molding compound acts as an intermediary material that provides a stable reference plane and mechanical support for the backside RDL formation. It compensates for minor variations in chip positioning and provides a consistent substrate for depositing the backside redistribution layers, thereby reducing the impact of alignment tolerances
Solution Approach 2:
The conductive pillars are designed to provide uniform electrical potential and mechanical support across the chip interface. By ensuring equipotential conditions at the connection interfaces, the system becomes more tolerant of minor alignment variations, as the electrical field distribution remains stable even with small positioning deviations
Data Source
AI summary
A package may include a first chip having a first surface and a second surface opposite the first surface; a first redistribution line (RDL) coupled to the first surface of the first chip; a second chip having a first surface and a second surface opposite the first surface, the first surface of the second chip facing the first chip; a second RDL disposed between the first chip and the second chip and coupled to the first surface of the second chip; a conductive via laterally adjacent to the second chip, the conductive via coupled to the second RDL; and a molding compound disposed between the second chip and the conductive via.