Multi-Chip Package Routing Structure With Reduced Layer Count
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packages face increased manufacturing difficulty and cost due to the need for finer pitch and more routing layers as the number of integrated semiconductor chips increases, leading to low yield.
Innovation Solution
A semiconductor package design featuring a coreless routing structure with a circuit member having a larger vertical projected area than the carrier structure, allowing for reduced layer count and improved yield, and incorporating a cladding layer for structural strength and warpage prevention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of integrated semiconductor chips is increased to achieve higher computing power and I/O expansion, then the functional performance is improved, but the pitch between conductive bumps decreases and the number of routing layers increases, leading to increased manufacturing difficulty and cost
Solution Approach 1:
The patent divides the routing function into two separate components: the carrier structure provides initial routing support, and the circuit member provides additional routing layers. This segmentation allows the routing functionality to be distributed across multiple independent structures, reducing the complexity burden on any single component and enabling higher I/O expansion without proportionally increasing overall manufacturing difficulty
Solution Approach 2:
The patent transitions from planar routing on the carrier structure to three-dimensional routing by adding the circuit member with multiple routing layers. This dimensional change enables signals to traverse through vertical stacking of routing layers in the circuit member, effectively increasing I/O capacity without linearly increasing the lateral routing complexity on the carrier structure
2Quantity of substance
If the pitch between conductive bumps is reduced to accommodate more chips, then the integration density is improved, but the manufacturing precision requirements increase significantly
Solution Approach 1:
The patent segments the chip array into multiple banks, where each bank has its own dedicated circuit member. This segmentation allows each circuit member to handle a subset of chips with moderate pitch requirements, rather than requiring a single circuit structure to accommodate all chips at high density. The overall integration density is maintained through parallel banking architecture
Solution Approach 2:
The circuit member acts as an intermediary structure between the carrier structure and the semiconductor chips. It provides an additional routing layer that mediates the connection between conductive bumps on different chips, allowing for more flexible signal routing that can accommodate varied bump pitches without directly increasing the precision requirements of the bump formation process itself
3Adaptability or versatility
If more routing layers are added to the carrier structure to connect more chips, then the connectivity is improved, but the manufacturing cost increases greatly
Solution Approach 1:
The patent segments the routing functionality between the carrier structure (providing base routing) and the circuit member (providing additional routing layers). This segmentation allows the expensive multi-layer routing to be concentrated in the dedicated circuit member rather than requiring the entire carrier structure to have high layer count, thereby reducing overall manufacturing cost while maintaining connectivity
Solution Approach 2:
The patent merges the carrier structure with the circuit member in a stacked configuration, where the circuit member is mounted on the carrier structure. This merging creates a unified routing system that combines the advantages of both structures: the carrier provides mechanical support and initial routing, while the circuit member adds routing capacity. The merged structure achieves high connectivity without requiring the carrier alone to have excessive routing layers
Data Source
AI summary
A method of manufacturing an electronic package is provided and includes disposing a circuit member and a plurality of electronic elements on opposite sides of a carrier structure having circuit layers respectively, so that any two of the plurality of electronic elements can be electrically connected to each other via the circuit layers and the circuit member, where a vertical projected area of the carrier structure is larger than a vertical projected area of the circuit member, such that the circuit member is free from being protruded from side surfaces of the carrier structure. Therefore, the circuit member replaces a part of circuit layers of the carrier structure to reduce the difficulty of fabricating the circuit layers in the carrier structure.