Multi-Chip Package Stress Relief Structure for CTE Warpage

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Solution Overview

Problem

The mismatch in coefficients of thermal expansion (CTE) between semiconductor dies and package substrates leads to warpage, die cracks, and delamination in semiconductor device packages, particularly during high-temperature processes like solder reflow, affecting yield and performance.

Innovation Solution

A stress relief structure is implemented by attaching a carrier substrate to the upper surface of a die group, which includes a fusion bond and may contain air gaps, to mitigate thermal stress. This structure compensates for height differences between die groups and reduces stress through the use of a carrier substrate with a trench and dielectric material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple dies with different CTEs are assembled into a multi-functional device, then device performance and functionality are improved, but thermal stress and warpage occur during solder reflow and operation

Engineering Contradiction:
Improvemulti-functional device performanceVSAvoidpackage substrate warpage and die cracks
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

A carrier substrate is introduced as an intermediary component between the package substrate and the die group. The carrier substrate has a CTE that is intermediate between the package substrate and the dies, serving as a stress buffer that reduces thermal mismatch stress during temperature cycling and solder reflow processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The package structure utilizes a composite material system consisting of the package substrate, carrier substrate, and dies with different CTEs. By carefully selecting materials with complementary properties and arranging them in a layered composite structure, the overall thermal stress is distributed and reduced

Inventive Principle:
Principle #40Composite materials

2Adaptability or versatility

If die groups with different heights are mounted on the package substrate, then multi-functional integration is achieved, but stress concentration and delamination occur

Engineering Contradiction:
Improvemulti-functional device integrationVSAvoidpackage substrate delamination
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The carrier substrate provides localized mechanical support and stress distribution under the die group. By configuring the carrier substrate with appropriate thickness and material properties in specific regions, it compensates for height differences between die groups and distributes stress locally to prevent delamination at the package substrate interface

Inventive Principle:
Principle #3Local quality

3Reliability

If a stress relief structure with carrier substrate is added, then thermal stress and warpage are reduced, but device complexity increases

Engineering Contradiction:
Improvethermal stress reductionVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The package structure is segmented into distinct functional layers: the package substrate providing electrical interconnection, the carrier substrate providing mechanical support and stress relief, and the die group providing functionality. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall system reliability

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress relief structure effectively reduces thermal stress and prevents warpage and delamination, enhancing the reliability and performance of semiconductor device packages.

Implementation Method 1

Different die groups and the package substrate have different coefficients of thermal expansion (CTEs). The significantly different CTEs may cause warpage in the package substrate at high temperatures

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

A stress relief structure is implemented by attaching a carrier substrate to the upper surface of a die group, which includes a fusion bond

Methodology Applied
Scientific EffectFusion bonding: Welding

Data Source

PatentUS20250279395A1Multi-chip package having stress relief structure
Publication Date: 2025.09.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250279395A1 patent drawing
  • US20250279395A1 patent drawing
  • US20250279395A1 patent drawing

AI summary

A semiconductor package is provided. The semiconductor package includes: a package substrate; a first die group having an upper surface and a lower surface opposite to each other and comprising a first plurality of dies, the lower surface of the first die group being directly bonded to the package substrate; a carrier substrate without any active electronic devices formed thereon and attached to the upper surface of the first die group and comprising a first air gap within the carrier substrate; a second die group comprising a second plurality of dies, the second die group being horizontally distal and distinct from the first die group and directly bonded to the package substrate; and a molding compound material disposed on the package substrate and encapsulating the first die group, the carrier substrate, and the second die group, wherein the molding compound material comprises a second air gap.