Multi-Chip Semiconductor Package With Through-Hole Substrate
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Solution Overview
Problem
Conventional semiconductor device packaging technologies face challenges with miniaturization, yield, reliability, and cost due to thermal expansion mismatch between silicon dies and PCBs, complex processes, and increased package size from redistribution layers and molding compounds.
Innovation Solution
A semiconductor device package structure featuring a substrate with die receiving through holes, adhesion materials, bonding wires, and a dielectric layer, where the substrate's thermal expansion coefficient matches the PCB's, allowing for a super thin, reliable, and cost-effective package with simplified processes and multi-chip integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional package technologies are used with silicon dies and molding compounds, then the package can be manufactured with standard processes, but the thermal expansion mismatch between silicon and molding compound causes reliability issues and yield problems
Solution Approach 1:
The substrate is designed with the same material composition as the PCB (epoxy substrate with glass fiber reinforcement), ensuring identical thermal expansion coefficients. This homogeneity eliminates differential thermal stress during temperature cycling, preventing solder joint fatigue and improving package reliability without requiring complex compensation structures.
2Volume of moving object
If wafer level package (WLP) technique is used to reduce package size, then the package dimensions are minimized, but the pin count increases and bonding points become too densely packed to meet PCB pitch requirements
Solution Approach 1:
The invention transitions from a two-dimensional surface-mount arrangement to a three-dimensional stacked configuration. Multiple dies are vertically stacked and interconnected through through-substrate vias, allowing high pin counts to be accommodated in the vertical dimension while maintaining a small footprint on the PCB. This enables both miniaturization and high I/O capacity simultaneously.
3Adaptability or versatility
If redistribution layers and molding compounds are added to conventional packages, then the package can accommodate more pins and provide protection, but the overall package size increases significantly
Solution Approach 1:
Multiple semiconductor dies are nested vertically within a compact substrate structure, with each die stacked above the previous one. This nesting approach allows multiple functional blocks to be integrated in a small volume by utilizing the vertical space, eliminating the need for lateral expansion through redistribution layers and molding compounds.
4Reliability
If conventional dicing and individual packaging processes are used, then each die can be packaged separately with proper testing, but the manufacturing process becomes time-consuming and costly
Solution Approach 1:
Multiple dies are mounted, interconnected, and packaged together as a single integrated unit on one substrate. This merging of multiple individual packaging operations into one simultaneous process dramatically increases manufacturing efficiency and reduces costs while maintaining quality through integrated testing and assembly.
Data Source
AI summary
The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.